Re: NuttX RTOS entirely in CPU Cache

I think a useful application could be in some microprocessors like Allwinner A10, A13, etc. It could be possible to create a board without DDR memory and use the internal cache as SRAM memory. For example A13 is low cost: https://aliexpress.com/item/1005001719371194.html has an easy to solder

Re: NuttX RTOS entirely in CPU Cache

Thank you Alan, this is a nice read, and it touches Cache as RAM (CAR), while I was thinking about putting whole RTOS inside cache :D L1 cache is the fastest memory possible, faster than L2, and a lot faster than DRAM/SRAM, that is faster than any storage drive :-) Just a curiosity :-) Tomek On

Re: NuttX RTOS entirely in CPU Cache

, Alan On Wed, May 21, 2025 at 4:49 PM Tomek CEDRO wrote: > Hello world :-) > > This post on LinkedIn by Laurie Laurie Kirk inspired me, as I know > Raiden is working on x86/AMD64 port of NuttX, and I have recenlty > upgraded my main desktop to Intel Ultra9 285K that has 36 MB Inte

NuttX RTOS entirely in CPU Cache

Hello world :-) This post on LinkedIn by Laurie Laurie Kirk inspired me, as I know Raiden is working on x86/AMD64 port of NuttX, and I have recenlty upgraded my main desktop to Intel Ultra9 285K that has 36 MB Intel Smart Cache / 40MB L2 Cache. Maybe a nice challenge to see it NuttX can run

About memory allocation for DMA on platforms with MMU/cache

Hi all, I am developing on an ARMv7-a Microchip SAMA5D2 board. When interacting with peripherals that have DMA capabilities, there are processes here and there to flush/invalidate the cache. However, I am seeing problems with various drivers that may not be handled properly. For example

Re: Cache

; arch/arm/src/armv7- > >a/ > > > >On 9/13/22, TimH wrote: > >> I will probably hit send then find it.but, right now, I can't see if > >> there's anything I need to do to enable DCACHE? > >> > >> > >> > >> My

RE: Cache

g has CONFIG_ARCH_DCACHE set, and that seems to "enable" all >> the various cache functions, including up_enable_dcache, but I can't >> find any calls to that function in sama5 related code. >> >> >> >> Any clues appreciated!! >> >> >> >>

Re: Cache

G_ARCH_DCACHE set, and that seems to "enable" all the > various cache functions, including up_enable_dcache, but I can't find any > calls to that function in sama5 related code. > > > > Any clues appreciated!! > > > >

Cache

I will probably hit send then find it.but, right now, I can't see if there's anything I need to do to enable DCACHE? My .config has CONFIG_ARCH_DCACHE set, and that seems to "enable" all the various cache functions, including up_enable_dcache, but I can't find any

Re: Nuttx Cortex-A/R SMP I-cache support

work queue work, and running Ostest many times. We would like to run both I-cache and D-cache enabled, but we spend some time trying to enable coherent d-caches with the SCU with no luck, and noticed some stability issues called out in the Sabre6 readme. So we settled on I-cache only. However

Nuttx Cortex-A/R SMP I-cache support

IMX6 as recent as February, 2020. Our current method of stress testing is to enable our features, which consist of some threads (around 6 or so) and low priority work queue work, and running Ostest many times. We would like to run both I-cache and D-cache enabled, but we spend some time trying