Re: [Article] NuttX on Star64 JH7110: RISC-V Privilege Levels and UART Registers

On Tue, Jul 18, 2023 at 10:34 PM Lee, Lup Yuen wrote: > Thanks Nathan! I'm still getting used to NuttX Kernel Mode and RISC-V > Machine / Supervisor Modes, so I thought I might stick with QEMU Kernel > Mode and make it work on Star64. > > But you're right, when I'm more familiar with Star64, I ou

Re: [Article] NuttX on Star64 JH7110: RISC-V Privilege Levels and UART Registers

Thanks Nathan! I'm still getting used to NuttX Kernel Mode and RISC-V Machine / Supervisor Modes, so I thought I might stick with QEMU Kernel Mode and make it work on Star64. But you're right, when I'm more familiar with Star64, I ought to explore more of CONFIG_ARCH_USE_S_MODE and RISC-V Machine

Re: [Article] NuttX on Star64 JH7110: RISC-V Privilege Levels and UART Registers

On Tue, Jul 18, 2023 at 7:33 PM Lee, Lup Yuen wrote: > We’re in the super-early stage of porting NuttX to the Pine64 Star64 64-bit > RISC-V SBC. (Based on StarFive JH7110 SoC) > > In this article we’ll talk about the interesting things that we learnt > about RISC-V and Star64 JH7110… > > (1) What

[Article] NuttX on Star64 JH7110: RISC-V Privilege Levels and UART Registers

We’re in the super-early stage of porting NuttX to the Pine64 Star64 64-bit RISC-V SBC. (Based on StarFive JH7110 SoC) In this article we’ll talk about the interesting things that we learnt about RISC-V and Star64 JH7110… (1) What are RISC-V Privilege Levels (And why they make NuttX a little