On 07/31/2013 11:18 AM, Thomas Monjalon wrote:
> The function rte_malloc_virt2phy has a dependency on rte_memory.h:
> phys_addr_t must be defined.
>
> The dependency handling for apps was wrong in the commit 8c86825cbf.
> Let's revert this part.
>
> Reported-by: Jia Sui
> Signed-off-by: Thomas Mon
On 04/15/2014 04:08 PM, Richardson, Bruce wrote:
>> -Original Message-
>> From: dev [mailto:dev-bounces at dpdk.org] On Behalf Of David Marchand
>> Sent: Tuesday, April 15, 2014 2:51 PM
>> To: dev at dpdk.org
>> Subject: [dpdk-dev] [PATCH 1/2] mem: add write memory barrier before
>> changin
Hello,
On 12/02/2014 07:52 AM, Jijiang Liu wrote:
> Replace the inner_l2_len and the inner_l3_len field with the outer_l2_len and
> outer_l3_len field, and rework csum forward engine and i40e PMD due to these
> changes.
>
> Signed-off-by: Jijiang Liu
[...]
> --- a/lib/librte_mbuf/rte_mbuf.h
>
ent, please contact
> the sender and delete all copies.
>
>
> --
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&g
> First setup_init_funcs() would just setup hw func pointers and wouldn't call
> e1000_init_nvm_params/ e1000_init_phy_params.
> Then we reset the lock, then call setup_funcs once again - that time it would
> read/write HW regs.
> Konstantin
>
> -Original Message---
Yes, i will add a new function that includes the lfence;
for the performance penalty, we did not see noticable performance impact
on our full software, so we did not see any reason to use 2 functions,
but it's certainly because we make a very limited number of calls to
rdtsc and it's true that
Hello,
I am testing testpmd on recent kernels (>= 3.15) and i have an IOMMU
problem (there are several commits around IOMMU in v3.15, they may be
related with this problem):
Hardware:
Platform: Intel S2600IP
CPU: Intel(R) Xeon(R) CPU E5-2697 v2 @ 2.70GHz
BIOS version: SE5C600.86B.02.03.0003.041
On 08/25/2015 08:52 PM, Vlad Zolotarov wrote:
>
> Helin, the issue has been seen on x540 devices. Pls., see a chapter
> 7.2.1.1 of x540 devices spec:
>
> A packet (or multiple packets in transmit segmentation) can span any
> number of
> buffers (and their descriptors) up to a limit of 40 minus WT
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