[PATCH v2 0/9] riscv: implement accelerated crc using zbc

ge - fix a bug in the net/ implementation that would cause segfaults on small unaligned buffers - refactor net/ implemementation to move variable declarations to top of functions - enable the optimisation in a couple other places optimised crc is preferred to jhash - l3fwd-power - cucko

[PATCH v2 1/9] config/riscv: detect presence of Zbc extension

to line up with this. The values returned by the interface are 64-bits long, so grow the hwcap registers array to be able to hold them. If the Zbc extension and intrinsics are both present and we can detect the Zbc extension at runtime, we define a flag, RTE_RISCV_FEATURE_ZBC. Signed-off-by:

[PATCH v2 2/9] hash: implement crc using riscv carryless multiply

also described here (https://web.archive.org/web/20240111232520/https://mary.rs/lab/crc32/) Add a case to the autotest_hash unit test. Signed-off-by: Daniel Gregory --- MAINTAINERS| 1 + app/test/test_hash.c | 7 +++ lib/hash/meson.build | 1 + lib/hash/rt

[PATCH v2 3/9] net: implement crc using riscv carryless multiply

repeated folds-by-1 whilst the buffer is still big enough, then perform Barrett's reductions on the rest. Add a case to the crc_autotest suite that tests this implementation. Signed-off-by: Daniel Gregory --- MAINTAINERS | 1 + app/test/test_crc.c | 9 ++ lib/net/meson.build |

[PATCH v2 4/9] config/riscv: add qemu crossbuild target

A new cross-compilation target that has extensions that DPDK uses and QEMU supports. Initially, this is just the Zbc extension for hardware crc support. Signed-off-by: Daniel Gregory --- config/riscv/meson.build| 3 ++- config/riscv/riscv64_qemu_linux_gcc

[PATCH v2 5/9] examples/l3fwd: use accelerated crc on riscv

When the RISC-V Zbc (carryless multiplication) extension is present, an implementation of CRC hashing using hardware instructions is available. Use it rather than jhash. Signed-off-by: Daniel Gregory --- examples/l3fwd/l3fwd_em.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[PATCH v2 6/9] ipfrag: use accelerated crc on riscv

When the RISC-V Zbc (carryless multiplication) extension is present, an implementation of CRC hashing using hardware instructions is available. Use it rather than jhash. Signed-off-by: Daniel Gregory --- lib/ip_frag/ip_frag_internal.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions

[PATCH v2 7/9] examples/l3fwd-power: use accelerated crc on riscv

When the RISC-V Zbc (carryless multiplication) extension is present, an implementation of CRC hashing using hardware instructions is available. Use it rather than jhash. Signed-off-by: Daniel Gregory --- examples/l3fwd-power/main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff

[PATCH v2 8/9] hash/cuckoo: use accelerated crc on riscv

When the RISC-V Zbc (carryless multiplication) extension is present, an implementation of CRC hashing using hardware instructions is available. Use it rather than jhash. Signed-off-by: Daniel Gregory --- lib/hash/rte_cuckoo_hash.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/lib/hash

[PATCH v2 9/9] member: use accelerated crc on riscv

When the RISC-V Zbc (carryless multiplication) extension is present, an implementation of CRC hashing using hardware instructions is available. Use it rather than jhash. Signed-off-by: Daniel Gregory --- lib/member/rte_member.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a

[PATCH v3 0/9] riscv: implement accelerated crc using zbc

r places optimised crc is preferred to jhash - l3fwd-power - cuckoo-hash Daniel Gregory (9): config/riscv: detect presence of Zbc extension hash: implement CRC using riscv carryless multiply net: implement CRC using riscv carryless multiply config/riscv: add qemu crossbuild tar

[PATCH v3 1/9] config/riscv: detect presence of Zbc extension

to line up with this. The values returned by the interface are 64-bits long, so grow the hwcap registers array to be able to hold them. If the Zbc extension and intrinsics are both present and we can detect the Zbc extension at runtime, we define a flag, RTE_RISCV_FEATURE_ZBC. Signed-off-by:

[PATCH v3 2/9] hash: implement CRC using riscv carryless multiply

also described here (https://web.archive.org/web/20240111232520/https://mary.rs/lab/crc32/) Add a case to the autotest_hash unit test. Signed-off-by: Daniel Gregory --- MAINTAINERS| 1 + app/test/test_hash.c | 7 +++ lib/hash/meson.build | 1 + lib/hash/rt

[PATCH v3 3/9] net: implement CRC using riscv carryless multiply

repeated folds-by-1 whilst the buffer is still big enough, then perform Barrett's reductions on the rest. Add a case to the crc_autotest suite that tests this implementation. Signed-off-by: Daniel Gregory --- MAINTAINERS | 1 + app/test/test_crc.c | 9 ++ lib/net/meson.build |

[PATCH v3 4/9] config/riscv: add qemu crossbuild target

A new cross-compilation target that has extensions that DPDK uses and QEMU supports. Initially, this is just the Zbc extension for hardware CRC support. Signed-off-by: Daniel Gregory --- config/riscv/meson.build| 3 ++- config/riscv/riscv64_qemu_linux_gcc

[PATCH v3 5/9] examples/l3fwd: use accelerated CRC on riscv

When the RISC-V Zbc (carryless multiplication) extension is present, an implementation of CRC hashing using hardware instructions is available. Use it rather than jhash. Signed-off-by: Daniel Gregory --- examples/l3fwd/l3fwd_em.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[PATCH v3 6/9] ipfrag: use accelerated CRC on riscv

When the RISC-V Zbc (carryless multiplication) extension is present, an implementation of CRC hashing using hardware instructions is available. Use it rather than jhash. Signed-off-by: Daniel Gregory --- lib/ip_frag/ip_frag_internal.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions

[PATCH v3 8/9] hash/cuckoo: use accelerated CRC on riscv

When the RISC-V Zbc (carryless multiplication) extension is present, an implementation of CRC hashing using hardware instructions is available. Use it rather than jhash. Signed-off-by: Daniel Gregory --- lib/hash/rte_cuckoo_hash.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/lib/hash

[PATCH v3 7/9] examples/l3fwd-power: use accelerated CRC on riscv

When the RISC-V Zbc (carryless multiplication) extension is present, an implementation of CRC hashing using hardware instructions is available. Use it rather than jhash. Signed-off-by: Daniel Gregory --- examples/l3fwd-power/main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff

[PATCH v3 9/9] member: use accelerated CRC on riscv

When the RISC-V Zbc (carryless multiplication) extension is present, an implementation of CRC hashing using hardware instructions is available. Use it rather than jhash. Signed-off-by: Daniel Gregory --- lib/member/rte_member.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a

[PATCH] eal/arm: replace RTE_BUILD_BUG on non-constant

‘RTE_BUILD_BUG_ON’ 156 | RTE_BUILD_BUG_ON(memorder != rte_memory_order_acquire && | ^~~~ This has been the case since the switch to C11 assert (537caad2). Fix the compile errors by replacing the check with an RTE_ASSERT. Signed-off-by: Daniel Gregory

[RFC PATCH] eal/riscv: add support for zawrs extension

olled by a Meson flag that is disabled by default. Signed-off-by: Daniel Gregory Suggested-by: Punit Agrawal --- Posting as an RFC to get early feedback and enable testing by others with Zawrs-enabled hardware. Whilst I have been able to test it compiles & passes tests using QEMU, I am w

Re: [PATCH] eal/arm: replace RTE_BUILD_BUG on non-constant

On Thu, May 02, 2024 at 09:20:45AM -0700, Stephen Hemminger wrote: > Why not: > diff --git a/lib/eal/arm/include/rte_pause_64.h > b/lib/eal/arm/include/rte_pause_64.h > index 5cb8b59056..81987de771 100644 > --- a/lib/eal/arm/include/rte_pause_64.h > +++ b/lib/eal/arm/include/rte_pause_64.h > @@ -1

Re: [PATCH] eal/arm: replace RTE_BUILD_BUG on non-constant

On Thu, May 02, 2024 at 02:48:26PM -0700, Stephen Hemminger wrote: > There are already constant checks like this elsewhere in the file. Yes, but they're in macros, rather than inlined functions, so my understanding was that at compile time, macro expansion has put the memorder constant in the _Sta

Re: [PATCH] eal/arm: replace RTE_BUILD_BUG on non-constant

On Fri, May 03, 2024 at 03:32:20PM +0200, David Marchand wrote: > - RTE_BUILD_BUG_ON() should not be used indeed. > IIRC, this issue was introduced with 875f350924b8 ("eal: add a new > helper for wait until scheme"). > Please add a corresponding Fixes: tag in next revision. Will do. Should I CC st

[PATCH v2] eal/arm: replace RTE_BUILD_BUG on non-constant

al: add a new helper for wait until scheme") Signed-off-by: Daniel Gregory --- Cc: feifei.wa...@arm.com --- lib/eal/arm/include/rte_pause_64.h | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/lib/eal/arm/include/rte_pause_64.h b/lib/eal/arm/include/rte_pause_64.

Re: [PATCH v2] eal/arm: replace RTE_BUILD_BUG on non-constant

Apologies, mis-sent this before attaching a changelog: v2: * replaced RTE_ASSERT with assert * added Fixes: tag

[PATCH] eal/arm: use stdatomic api in rte_pause

Missed during commit 1ec6a845b5cb ("eal: use stdatomic API in public headers") Signed-off-by: Daniel Gregory --- lib/eal/arm/include/rte_pause_64.h | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/lib/eal/arm/include/rte_pause_64.h b/lib/eal/arm/include/rte_

Re: [PATCH] eal/arm: replace RTE_BUILD_BUG on non-constant

On Fri, May 03, 2024 at 05:56:24PM -0700, Stephen Hemminger wrote: > On Fri, 3 May 2024 10:46:05 +0100 > Daniel Gregory wrote: > > > On Thu, May 02, 2024 at 02:48:26PM -0700, Stephen Hemminger wrote: > > > There are already constant checks like this elsewhere in the f

Re: [PATCH] eal/arm: replace RTE_BUILD_BUG on non-constant

On Fri, May 03, 2024 at 06:02:36PM -0700, Stephen Hemminger wrote: > On Thu, 2 May 2024 15:21:16 +0100 > Daniel Gregory wrote: > > > The ARM implementation of rte_pause uses RTE_BUILD_BUG_ON to check > > memorder, which is not constant. This causes compile errors when i

Re: [RFC PATCH] eal/riscv: add support for zawrs extension

On Sun, May 12, 2024 at 09:10:49AM +0200, Stanisław Kardach wrote: > On Thu, May 2, 2024 at 4:44 PM Daniel Gregory > wrote: > > diff --git a/config/riscv/meson.build b/config/riscv/meson.build > > index 07d7d9da23..4cfdc42ecb 100644 > > --- a/config/riscv/meson.buil

[PATCH 0/2] eal/riscv: implement prefetch using zicbop

ports this extension, so I haven't tested how this affects performance yet. Daniel Gregory (2): eal: add flag to hide generic prefetch_write eal/riscv: add support for zicbop extension config/riscv/meson.build | 6 +++ lib/eal/include/generic/rte_prefe

[PATCH 1/2] eal: add flag to hide generic prefetch_write

This allows for the definition of architecture-specific implementations of the rte_prefetch*_write collection of functions by defining RTE_PREFETCH_WRITE_ARCH_DEFINED. Signed-off-by: Daniel Gregory --- lib/eal/include/generic/rte_prefetch.h | 47 +- 1 file changed, 31

[PATCH 2/2] eal/riscv: add support for zicbop extension

y be costly. Signed-off-by: Daniel Gregory Suggested-by: Punit Agrawal --- config/riscv/meson.build | 6 +++ lib/eal/riscv/include/rte_prefetch.h | 57 ++-- 2 files changed, 59 insertions(+), 4 deletions(-) diff --git a/config/riscv/meson.build b/config/ris

Re: [PATCH 2/2] eal/riscv: add support for zicbop extension

On Thu, May 30, 2024 at 06:19:48PM +0100, Daniel Gregory wrote: > + * The RTE_RISCV_ZICBOP option controls whether we emit them manually for > older > + * compilers that may not have the support to assemble them. > + */ > static inline void rte_prefetch0(const v

[PATCH 0/5] riscv: implement accelerated crc using zbc

6 | 932736 |68023 | 437016 | 107726 | |7 | 1088756 |79236 | 510197 | 125426 | |8 | 1243794 |90467 | 583231 | 143614 | These results suggest a speed-up of lib/net by thirteen times, and of lib/hash by four times. Daniel Gregory (5): config/riscv: add fla

[PATCH 1/5] config/riscv: add flag for using Zbc extension

The RISC-V Zbc extension adds carry-less multiply instructions we can use to implement more efficient CRC hashing algorithms. Signed-off-by: Daniel Gregory --- config/riscv/meson.build | 7 +++ 1 file changed, 7 insertions(+) diff --git a/config/riscv/meson.build b/config/riscv/meson.build

[PATCH 2/5] hash: implement crc using riscv carryless multiply

also described here (https://web.archive.org/web/20240111232520/https://mary.rs/lab/crc32/) Signed-off-by: Daniel Gregory --- MAINTAINERS| 1 + app/test/test_hash.c | 7 +++ lib/hash/meson.build | 1 + lib/hash/rte_crc_riscv64.h | 89

[PATCH 3/5] net: implement crc using riscv carryless multiply

repeated folds-by-1 whilst the buffer is still big enough, then perform Barrett's reductions on the rest. Add a case to the crc_autotest suite that tests this implementation. This implementation is enabled by setting the RTE_RISCV_ZBC flag (see config/riscv/meson.build). Signed-off-by: Daniel

[PATCH 4/5] examples/l3fwd: use accelerated crc on riscv

When the RISC-V Zbc (carryless multiplication) extension is present, an implementation of CRC hashing using hardware instructions is available. Use it rather than jhash. Signed-off-by: Daniel Gregory --- examples/l3fwd/l3fwd_em.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[PATCH 5/5] ipfrag: use accelerated crc on riscv

When the RISC-V Zbc (carryless multiplication) extension is present, an implementation of CRC hashing using hardware instructions is available. Use it rather than jhash. Signed-off-by: Daniel Gregory --- lib/ip_frag/ip_frag_internal.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions

RE: [PATCH 1/5] config/riscv: add flag for using Zbc extension

On Wed, Jun 19, 2024 at 09:08:14AM +0200, Morten Brørup wrote: > > From: Stephen Hemminger [mailto:step...@networkplumber.org] > 1/5] config/riscv: add flag for using Zbc extension > > > > On Tue, 18 Jun 2024 18:41:29 +0100 > > Daniel Gregory wrote: > >

Re: [PATCH v2] eal/arm: replace RTE_BUILD_BUG on non-constant

On Thu, Jun 27, 2024 at 05:08:51PM +0200, Thomas Monjalon wrote: > 04/05/2024 02:59, Stephen Hemminger: > > On Fri, 3 May 2024 19:27:30 +0100 > > Daniel Gregory wrote: > > > > > The ARM implementation of rte_pause uses RTE_BUILD_BUG_ON to check > > > memor

Re: [PATCH v3 0/9] riscv: implement accelerated crc using zbc

Would it be possible to get a review on this patchset? I would be happy to hear any feedback on the approach to RISC-V extension detection or how I have implemented the hardware-optimised CRCs. Kind regards, Daniel