64. NUM_RX_DESC is 128 (I've tried with larger values).
The NIC is an Intel 82599 10GbE, DPDK version is 1.5.
--Anuj Kalia
Vladimir,
Few possible fixes to your PCIe analysis (let me know if I'm wrong):
- ECRC is probably disabled (check using sudo lspci -vvv | grep
CGenEn-), so TLP header is 26 bytes
- Descriptor writeback can be batched using high value of WTHRESH,
which is what DPDK uses by default
- Read request co
32) / 4
> (batched descriptor writeback)
> , thus we have 135 bytes/packet
>
> This corresponds to 58.8 Mpps
>
> Regards,
> Vladimir
>
> 2015-07-01 17:22 GMT+03:00 Anuj Kalia :
>>
>> Vladimir,
>>
>> Few possible fixes to your PCIe analysis (let me know
Hi Parikshith.
A CPU core can have a limited number of prefetches in flight (around 10).
So if you issue 64 (or nb_rx > 10) prefetches in quick succession, you'll
stall on memory access. The main idea here is to overlap prefetches of some
packets with computation from other packets.
This paper ex
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