This patchset add rte_flow support for cpfl driver.
It depends on the following two patch sets:
http://patchwork.dpdk.org/project/dpdk/cover/20230809155134.539287-1-beilei.x...@intel.com/
http://patchwork.dpdk.org/project/dpdk/cover/20230811100012.2078135-1-wenjing.q...@intel.com/
Yuying Zhang (5)
Setup the rte_flow backend skeleton. Introduce the framework
to support different engines as rte_flow backend. Bridge rte_flow
driver API to flow engines.
Signed-off-by: Yuying Zhang
Signed-off-by: Qi Zhang
---
drivers/net/cpfl/cpfl_ethdev.c | 54 ++
drivers/net/cpfl/cpfl_ethdev.h | 5 +
Add cfg data in idpf_ctlq_msg.
Signed-off-by: Yuying Zhang
---
drivers/common/idpf/base/idpf_controlq_api.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/common/idpf/base/idpf_controlq_api.h
b/drivers/common/idpf/base/idpf_controlq_api.h
index 3780304256..b38b10465c 100644
---
Add cpfl driver control queue message handle, including
send/receive/clean/post_rx_buffs.
Signed-off-by: Yuying Zhang
---
drivers/net/cpfl/cpfl_controlq.c | 419 ++-
drivers/net/cpfl/cpfl_controlq.h | 24 ++
2 files changed, 442 insertions(+), 1 deletion(-)
diff --g
Added low level fxp module for rule packing / creation / destroying.
Signed-off-by: Yuying Zhang
---
drivers/net/cpfl/cpfl_ethdev.h | 4 +
drivers/net/cpfl/cpfl_fxp_rule.c | 288 +++
drivers/net/cpfl/cpfl_fxp_rule.h | 87 ++
drivers/net/cpfl/meson.build
Adapt fxp low level as a flow engine.
Signed-off-by: Yuying Zhang
Signed-off-by: Qi Zhang
---
drivers/net/cpfl/cpfl_ethdev.h | 85
drivers/net/cpfl/cpfl_flow_engine_fxp.c | 610
drivers/net/cpfl/meson.build| 1 +
3 files changed, 696 inserti
[AMD Official Use Only - General]
> > > >
> > > > From last email from my end `we should promote and document the
> > > changes provided the existing tool is phased out and use lstopo`.
> > > >
> > > > Note:
> > > > 1. This is with assumption that both Linux and Windows `lstopo` is
> > > > modif
On Sat, 12 Aug 2023 06:27:20 +0530
Vipin Varghese wrote:
> Most modern processor now supports numa by partitioning
> NUMA based on CPU-IO & Last Level Cache within the same socket.
> As per the discussion in mailing list, suggesting the make
> use of hw-loc for such scenarios.
>
> Signed-off-by:
[AMD Official Use Only - General]
> -Original Message-
> From: Stephen Hemminger
> Sent: Saturday, August 12, 2023 8:30 PM
> To: Varghese, Vipin
> Cc: tho...@monjalon.net; dev@dpdk.org; Yigit, Ferruh
>
> Subject: Re: [PATCH] usertools: suggest use of hwloc for new cpu
>
> Caution: This
Hi Wenwu,
On 8/7/2023 7:28 AM, Wenwu Ma wrote:
When doing IO port mapping for legacy device
in secondary process, the region information
is missing, so, we need to refill it.
Fixes: 4b741542ecde ("bus/pci: avoid depending on private kernel value")
Cc: sta...@dpdk.org
Signed-off-by: Wenwu Ma
-
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