By triggerring the VF reset from PF reset,
echo 1 > /sys/bus/pci/devices/PF-BDF/reset
the PCI bus master bit will cleared on VF, so the VF needs to enable
this bit before restart.
This patch set adds the API to enable PCI bus master.
v6: update the annotate symbol version, and add some
Add the API to set 'Bus Master Enable' bit to be enabled or disabled in
the PCI command register.
Signed-off-by: Haiyue Wang
Acked-by: Ray Kinsella
---
drivers/bus/pci/pci_common.c | 28
drivers/bus/pci/rte_bus_pci.h | 14 ++
drivers/bus/pci/version.map
The VF reset can be triggerred by the PF reset event, in this case, the
PCI bus master will be cleared, then the VF is not allowed to issue any
Memory or I/O Requests.
So after the reset event is detected, always enable the PCI bus master.
And if failed, the device or system may be in an invalid s
The VF reset can be triggerred by the PF reset event, in this case, the
PCI bus master will be cleared, then the VF is not allowed to issue any
Memory or I/O Requests.
So after the reset event is detected, always enable the PCI bus master.
And if failed, the device or system may be in an invalid s
Trigger the VF reset from PF reset,
echo 1 > /sys/bus/pci/devices/PF-BDF/reset
the PCI bus master bit will cleared on VF, so the VF needs to enable
this bit before restart.
This patch set adds the API to enable PCI bus master.
v7: fix the commit message typo, and update some description
Add the API to set 'Bus Master Enable' bit to be enabled or disabled in
the PCI command register.
Signed-off-by: Haiyue Wang
Acked-by: Ray Kinsella
---
drivers/bus/pci/pci_common.c | 28
drivers/bus/pci/rte_bus_pci.h | 14 ++
drivers/bus/pci/version.map
The VF reset can be triggered by the PF reset event, then the PCI bus
master will be cleared, the VF will be not allowed to issue any Memory
or I/O Requests.
So after the reset event is detected, always enable the PCI bus master.
And if failed, the device or system may be in an invalid state, so k
The VF reset can be triggered by the PF reset event, then the PCI bus
master will be cleared, the VF will be not allowed to issue any Memory
or I/O Requests.
So after the reset event is detected, always enable the PCI bus master.
And if failed, the device or system may be in an invalid state, so k
> -Original Message-
> From: Yang, SteveX
> Sent: Wednesday, May 19, 2021 11:28 AM
> To: dev@dpdk.org
> Cc: Xing, Beilei ; Yang, SteveX
> Subject: [PATCH v1] net/i40e: fix flow director does not work
>
> When user configured the flow rule with raw packet via command
> "flow_director_f
> -Original Message-
> From: fengchengwen
> Sent: Friday, May 21, 2021 2:53 PM
> To: Ruifeng Wang ; tho...@monjalon.net;
> ferruh.yi...@intel.com
> Cc: dev@dpdk.org; jer...@marvell.com; vikto...@rehivetech.com;
> bruce.richard...@intel.com; Honnappa Nagarahalli
> ; jerinjac...@gmail.com;
>
Hi mlnx teams,
How can I enable VF LAG with switch mode in the upstrem dpdk?
echo 1 > /sys/class/net/net2/device/sriov_numvfs
echo 1 > /sys/class/net/net3/device/sriov_numvfs
echo :19:00.2 > /sys/bus/pci/drivers/mlx5_core/unbind
echo :19:08.1 > /sys/bus/pci/drivers/mlx5_core/unbind
de
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