Hi,
> -Original Message-
> From: dev On Behalf Of David Marchand
> Sent: Wednesday, October 2, 2019 5:24 PM
> To: dev@dpdk.org
> Cc: sta...@dpdk.org; Matan Azrad ; Shahaf Shuler
>
> Subject: [dpdk-dev] [PATCH] net/mlx4: remove dependency on libmnl in
> meson
>
> There is no dependency o
Hi,
> -Original Message-
> From: Viacheslav Ovsiienko
> Sent: Monday, October 14, 2019 6:39 PM
> To: dev@dpdk.org
> Cc: Matan Azrad ; Raslan Darawsheh
> ; sta...@dpdk.org
> Subject: [PATCH] net/mlx5: fix transmitted packets statistics counter
>
> The transmitter packets counter was not u
Hi,
> -Original Message-
> From: dev On Behalf Of Ali Alnubani
> Sent: Tuesday, October 15, 2019 5:56 PM
> To: dev@dpdk.org
> Cc: Slava Ovsiienko ; Jeremy Plsek
>
> Subject: [dpdk-dev] [PATCH] net/mlx5: fix build with strict alignment enabled
>
> This patch converts some of the casts to
Hi,
> -Original Message-
> From: Moti Haimovsky
> Sent: Wednesday, October 16, 2019 10:34 AM
> To: Slava Ovsiienko ; Raslan Darawsheh
>
> Cc: dev@dpdk.org
> Subject: [PATCH v2] net/mlx5: retry when link update fails
>
> mlx5_link_update immediately returns when called with no-wait parame
Hi,
> -Original Message-
> From: Moti Haimovsky
> Sent: Wednesday, October 16, 2019 11:36 AM
> To: Slava Ovsiienko ; Raslan Darawsheh
>
> Cc: dev@dpdk.org
> Subject: [PATCH 1/2] net/mlx5: query HCA for enabled FLEX parser protos
>
> This commit add querying the HCA which FLEX protocols
On x86, iopl permissions are only available to root user (or users that
have the CAP_SYS_RAWIO capability).
But those permissions are only needed when the virtio devices accesses
are done with inb/outb instructions, which is when the device is bound
to a UIO kernel module.
So far, the virtio drive
Here are two little changes to be able to run testpmd as non-root with
virtio ports in a guest.
This requires a functional vIOMMU (the main pain parts being writing a
Q35 machine configuration in qemu for x86 guests).
No major change since the RFC, I just did not find the time to describe
the full
On x86, calling inb/outb special instructions (used in UIO ioport
read/write parts) is only possible if the right IO permissions has been
granted.
The only user of this API (the net/virtio pmd) checks this
unconditionnaly but this should be hidden by the rte_pci_ioport API
itself and only checked
Hi,
Replaying here because I can't find the first email in the thread.
Regarding testing results with Mellanox devices, we did basic functional
testing with testpmd, and don't see any issues.
Testing matrix:
- NIC: ConnectX-5 / OS: RHEL 7.4 / Kernel: 5.3.0 / Driver: rdma-core v25.1 /
fw: 16.26
On Sun, Oct 20, 2019 at 10:22 AM wrote:
>
> From: Kiran Kumar K
>
> Add new rte_flow_item_higig2_hdr in order to match higig2 header.
> It is a layer 2.5 protocol and used in Broadcom switches.
> Header format is based on the following document.
> http://read.pudn.com/downloads558/doc/comm/230146
On 10/16/2019 9:36 AM, Moti Haimovsky wrote:
> This commit adds support for matching flows on Geneve headers.
>
> Signed-off-by: Moti Haimovsky
<...>
> --- a/doc/guides/rel_notes/release_19_11.rst
> +++ b/doc/guides/rel_notes/release_19_11.rst
> @@ -286,4 +286,5 @@ Tested Platforms
>* Added
> -Original Message-
> From: Wang Xiang
> Sent: Monday, October 14, 2019 7:29 PM
> To: Jerin Jacob Kollanukkaran
> Cc: Thomas Monjalon ; dev@dpdk.org; Pavan
> Nikhilesh Bhagavatula ; Shahaf Shuler
> ; Hemant Agrawal ;
> Opher Reviv ; Alex Rosenbaum
> ; Dovrat Zifroni ; Prasun Kapoor
> ; N
Add performance tests for rte_ring_xxx_elem APIs. At this point these
are derived mainly from existing rte_ring_xxx test cases.
Signed-off-by: Honnappa Nagarahalli
---
app/test/Makefile | 1 +
app/test/meson.build | 1 +
app/test/test_ring_perf_elem.c | 419 +++
Add functional tests for rte_ring_xxx_elem APIs. At this point these
are derived mainly from existing rte_ring_xxx test cases.
Signed-off-by: Honnappa Nagarahalli
---
app/test/Makefile | 1 +
app/test/meson.build | 1 +
app/test/test_ring_elem.c | 859 +++
The current rte_ring hard-codes the type of the ring element to 'void *',
hence the size of the element is hard-coded to 32b/64b. Since the ring
element type is not an input to rte_ring APIs, it results in couple
of issues:
1) If an application requires to store an element which is not 64b, it
Use division instead of modulo operation to calculate more
accurate cycle count.
Signed-off-by: Honnappa Nagarahalli
---
app/test/test_ring_perf.c | 22 --
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/app/test/test_ring_perf.c b/app/test/test_ring_perf.c
in
Current APIs assume ring elements to be pointers. However, in many
use cases, the size can be different. Add new APIs to support
configurable ring element sizes.
Signed-off-by: Honnappa Nagarahalli
Reviewed-by: Dharmik Thakkar
Reviewed-by: Gavin Hu
Reviewed-by: Ruifeng Wang
---
lib/librte_rin
Copy of ring elements uses memcpy for 32B chunks. The remaining
bytes are copied using assignments.
Signed-off-by: Honnappa Nagarahalli
---
lib/librte_ring/rte_ring.c | 10 --
lib/librte_ring/rte_ring_elem.h | 229 +++-
2 files changed, 49 insertions(+), 190 del
Improved copy function to copy to/from ring elements.
Signed-off-by: Honnappa Nagarahalli
Signed-off-by: Konstantin Ananyev
---
lib/librte_ring/rte_ring_elem.h | 165
1 file changed, 84 insertions(+), 81 deletions(-)
diff --git a/lib/librte_ring/rte_ring_elem.h
> > >
> > > > Subject: Re: [PATCH v4 1/2] lib/ring: apis to support configurable
> > > > element size
> > > >
> > > > >>> I tried this. On x86 (Xeon(R) Gold 6132 CPU @ 2.60GHz), the
> > > > >>> results are as
> > > > >> follows. The numbers in brackets are with the code on master.
> > > > >>> gcc (
>
> Hi everyone,
>
>
> > > > >>> I tried this. On x86 (Xeon(R) Gold 6132 CPU @ 2.60GHz), the
> > > > >>> results are as
> > > > >> follows. The numbers in brackets are with the code on master.
> > > > >>> gcc (Ubuntu 7.4.0-1ubuntu1~18.04.1) 7.4.0
> > > > >>>
> > > > >>> RTE>>ring_perf_elem_autot
Hi, Ferruh,
Thanks for your advice. I will move the header info into rte_ether.h. It could
be better.
-Original Message-
From: Yigit, Ferruh
Sent: Saturday, October 19, 2019 2:50 AM
To: Xu, Ting ; dev@dpdk.org
Cc: Lu, Wenzhuo ; Wu, Jingjing ;
Iremonger, Bernard ; Zhang, Qi Z
Subject:
Hi, Olivier,
Thanks for advice. I will modify codes according to your comments.
As for the packet header, I define a simplified GTP header in patch:
app/testpmd: enable GTP header parse and Tx checksum offload, in order to help
forward GTP packet in testpmd.
I just moved some codes to rte_ether.
Vlan packets with ip length bigger then 1496 will not be received by
i40e/i40evf due to wrong packets size checking. This patch fixes the issue
by correcting the maximum frame size during checking.
Fixes: 43e5488c0ac6 ("net/i40e: support MTU configuration")
Cc: sta...@dpdk.org
Signed-off-by: Xiao
In this patchset, minor modifications are made in ice pmd and
mbuf to support GTP Tx checksum offload in CVL. Add the GTP
tunnel type flag in mbuf.
v2: modify codes according to comments. Add flag name in
rte_mbuf.c.
Ting Xu (2):
lib/mbuf: add GTP tunnel type flag
net/ice: add GTP tunnel type
Add GTP tunnel type flag in mbuf for future use in GTP
Tx checksum offload.
Signed-off-by: Ting Xu
---
lib/librte_mbuf/rte_mbuf.c | 2 ++
lib/librte_mbuf/rte_mbuf.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/lib/librte_mbuf/rte_mbuf.c b/lib/librte_mbuf/rte_mbuf.c
index 0236fba76..952
Add GTP tunnel type in ice pmd tunneling parameters parse
to enable Tx checksum offload.
Signed-off-by: Ting Xu
---
doc/guides/rel_notes/release_19_11.rst | 1 +
drivers/net/ice/ice_rxtx.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/doc/guides/rel_notes/release_19_11.rst
b
Hi Pavan,
snipped
>
> Add graceful teardown that addresses both event mode and poll mode.
>
> Signed-off-by: Pavan Nikhilesh
> ---
snipped
> + if (rsrc->event_mode) {
> + struct l2fwd_event_resources *evt_rsrc =
> + rsrc->evt_r
HI Pavan,
snipped
> Add event dev main loop based on enabled l2fwd options and eventdev
> capabilities.
>
> Signed-off-by: Pavan Nikhilesh
> ---
> + if (rsrc->event_mode) {
> + port_conf.rxmode.mq_mode = ETH_MQ_RX_RSS;
> + port_conf.rx_adv_conf.rss_conf.rss_key = NULL
Hi Pavan,
Thanks for sharing the write up, following are some of my thoughts.
Snipped
>
> Based on event device capability the configuration is done as follows:
> - A single event device is enabled.
> - The number of event ports is equal to the number of worker
> cores enabled in t
HI Pavan,
snipped
> +
> +/* Print out statistics on packets dropped */ void print_stats(struct
> +l2fwd_resources *rsrc) {
> + uint64_t total_packets_dropped, total_packets_tx, total_packets_rx;
> + uint32_t port_id;
> +
> + total_packets_dropped = 0;
> + total_packets_tx = 0;
> +
From: Kiran Kumar K
Add new rte_flow_item_higig2_hdr in order to match higig2 header.
It is a layer 2.5 protocol and used in Broadcom switches.
Header format is based on the following document.
http://read.pudn.com/downloads558/doc/comm/2301468/HiGig_protocol.pdf
Signed-off-by: Kiran Kumar K
Ac
> -Original Message-
> From: dev On Behalf Of Xiaoyu Min
> Sent: Thursday, October 17, 2019 13:50
> To: Shahaf Shuler ; Yongseok Koh
>
> Cc: dev@dpdk.org; sta...@dpdk.org; Zengmo Gao
> Subject: [dpdk-dev] [PATCH] net/mlx5: fix segfault when create hash rxq of
> drop
>
> When to create h
Hi Conole,
Thanks.
It will be included in next version.
-Original Message-
From: Aaron Conole [mailto:acon...@redhat.com]
Sent: Monday, October 14, 2019 10:40 PM
To: Pei, Andy
Cc: dev@dpdk.org; Xu, Rosen ; Zhang, Tianfei
; Ye, Xiaolong ; Zhang, Qi Z
Subject: Re: [dpdk-dev] [PATCH v9
This patch enables testpmd to forward GTP packet in csum fwd mode.
GTP header structure (without optional fields and extension header)
and parser function are added. GTPU and GTPC packets are both
supported, with respective UDP destination port and GTP message
type.
Signed-off-by: Ting Xu
---
v4
Hi, Xiaolong
Thanks.
This will be fixed in v10.
-Original Message-
From: Ye, Xiaolong
Sent: Saturday, October 19, 2019 8:57 AM
To: Pei, Andy
Cc: dev@dpdk.org; Xu, Rosen ; Zhang, Tianfei
; Zhang, Qi Z
Subject: Re: [PATCH v9 13/18] raw/ifpga/base: add secure support
On 10/14, Andy Pei
CAAM JR can work on both LE and BE mode.
Latest platforms are in LE mode, so changing the
default mode to LE to make it more convenient for
the latest platforms.
Signed-off-by: Gagandeep Singh
---
config/defconfig_arm64-dpaa-linuxapp-gcc | 3 ---
doc/guides/cryptodevs/caam_jr.rst| 4 ++--
On 10/09, Harry van Haaren wrote:
>v2:
>- Improve RSS clearning in SSE 16B descriptor
>- Fix AVX 16B descriptor data handling
>
>---
>
>Hey All,
>
>This series adds FDIR ID support to the vector Rx routines.
>Support for both the SSE and AVX drivers is added, and both
>the 16 byte and 32 byte descr
This patch set adds PCIe AER disable and FPGA interrupt support for
ipn3ke. It also provides a small rework for port bonding between FPGA
line side port and I40e PF port.
What is the PCI Express AER(Advanced Error Reporting)?
Advanced Error Reporting capability is implemented with a PCI Express
From: Tianfei zhang
Every defined bit in FME_ERROR0 is RW1C. Other reserved bits are always
0 when readout and it will plan to be RW1C if needed in future.
So it is safe just write the read back value to clear all the errors.
Signed-off-by: Tianfei zhang
Signed-off-by: Andy Pei
---
drivers/ra
From: Tianfei zhang
This patch exposes SEU error information to application then application
could compare this information (128bit) with its own SMH file to know
if this SEU is a fatal error or not.
Signed-off-by: Tianfei zhang
Signed-off-by: Andy Pei
---
drivers/raw/ifpga/base/ifpga_defines
In ipn3ke, each FPGA network side port bonding to an i40e pf,
each i40e pf link status should get data from FPGA network,
side port. This patch provide bonding relationship.
Signed-off-by: Rosen Xu
Signed-off-by: Andy Pei
---
drivers/net/i40e/base/i40e_type.h | 3 +++
drivers/net/i40e/
From: Tianfei zhang
Add irq support for ifpga FME global error, port error and uint unit.
We implmented this feature by vfio interrupt mechanism.
To build this feature, CONFIG_RTE_EAL_VFIO should be enabled.
Signed-off-by: Tianfei zhang
Signed-off-by: Andy Pei
---
config/common_base
From: Tianfei zhang
In PAC N3000 card, this is a BMC chip which using MAX10 FPGA
to manage the board configuration, like sensors, flash controller,
QSFP, powers. And this is a SPI bus connected between A10 FPGA and
MAX10, we can access the MAX10 registers over this SPI bus.
In BMC, there are abo
From: Tianfei zhang
The length of send buffer of SPI bus should be 4bytes align.
Signed-off-by: Tianfei Zhang
Signed-off-by: Andy Pei
---
drivers/raw/ifpga/base/opae_spi_transaction.c | 40 ---
1 file changed, 36 insertions(+), 4 deletions(-)
diff --git a/drivers/raw/
From: Tianfei zhang
The sensor devices are connected in MAX10 FPGA. we used the
device tree to describe those sensor devices. Parse the device
tree to get the sensor devices and add them into a list.
Signed-off-by: Tianfei zhang
Signed-off-by: Andy Pei
---
drivers/raw/ifpga/base/opae_intel_ma
From: Tianfei zhang
Introducing sensor APIs to PMD driver for PAC N3000 card.
Those sensor APIs:
1. opae_mgr_for_each_sensor()
2. opae_mgr_get_sensor_by_name()
3. opae_mgr_get_sensor_by_id()
4. opae_mgr_get_sensor_value_by_name()
5. opae_mgr_get_sensor_value_by_id()
6. opae_mgr_get_sensor_value(
From: Rosen Xu
Add PCIe BDF devices tree scan for ipn3ke.
Signed-off-by: Rosen Xu
Signed-off-by: Andy Pei
---
drivers/raw/ifpga/ifpga_rawdev.c | 551 ++-
drivers/raw/ifpga/ifpga_rawdev.h | 16 ++
2 files changed, 562 insertions(+), 5 deletions(-)
diff --g
From: Tianfei zhang
Update the SEU registser definition.
Signed-off-by: Tianfei zhang
Signed-off-by: Andy Pei
---
drivers/raw/ifpga/base/ifpga_defines.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/raw/ifpga/base/ifpga_defines.h
b/drivers/raw/ifpga/base/ifpg
From: Rosen Xu
Add SEU interrupt support for FPGA.
Signed-off-by: Tianfei zhang
Signed-off-by: Rosen Xu
Signed-off-by: Andy Pei
---
drivers/raw/ifpga/ifpga_rawdev.c | 245 +++
1 file changed, 245 insertions(+)
diff --git a/drivers/raw/ifpga/ifpga_rawdev.c
From: Rosen Xu
The ipn3ke board FPGA and i40e BDF scan has added in ifpga_rawdev,
so it doesn't need to provide configuration for i40e port bonding.
Signed-off-by: Rosen Xu
Signed-off-by: Andy Pei
---
drivers/meson.build| 7 +-
drivers/net/ipn3ke/Makefile
From: Tianfei zhang
We can change the PKVL FEC mode when the A10 NIOS FW
initialization. The end-user can use this feature the
change the FEC mode, the default mode is RS FEC mode.
Signed-off-by: Tianfei zhang
Signed-off-by: Andy Pei
---
drivers/raw/ifpga/base/ifpga_fme.c | 42 +++
From: Tianfei zhang
Clean fme errors register when some fme errors occurred.
Signed-off-by: Tianfei zhang
Signed-off-by: Andy Pei
---
drivers/raw/ifpga/base/ifpga_fme_error.c | 24 ++--
drivers/raw/ifpga/ifpga_rawdev.c | 22 ++
2 files changed,
From: Tianfei zhang
Add secure max10 device support.
Signed-off-by: Tianfei zhang
Signed-off-by: Andy Pei
---
drivers/raw/ifpga/base/ifpga_defines.h| 2 +
drivers/raw/ifpga/base/ifpga_fme.c| 26 --
drivers/raw/ifpga/base/opae_intel_max10.c | 137 +---
From: Tianfei zhang
In PAC N3000 card, there is one MAX10 chip in each card, and
all of the sensors are connected to MAX10 chip. To support multiple
cards in one server, we introducing a sensor device list under
intel_max10_device instead of a global list. On the other hand, we
using separate int
if fpga image support lightweight feature, set afu uuid to all 0, ipn3ke
representor will not be probed.
Signed-off-by: Andy Pei
---
drivers/raw/ifpga/ifpga_rawdev.c | 44 +---
1 file changed, 32 insertions(+), 12 deletions(-)
diff --git a/drivers/raw/ifpga/i
From: Tianfei zhang
Add new API to get the board info.
opae_mgr_get_board_info()
Signed-off-by: Tianfei zhang
Signed-off-by: Andy Pei
---
drivers/raw/ifpga/base/ifpga_api.c | 11 +++
drivers/raw/ifpga/base/ifpga_defines.h | 55 ++
drivers/raw/ifpga/base
From: Tianfei zhang
Introducing new register and unregister API for ifpga interrupt.
1. register FME and AFU interrupt
ifpga_register_msix_irq()
2. unregister FME and AFU interrupt
ifpga_unregister_msix_irq()
On PAC N3000 card, there is one PCIe MSIX interrupt for FME managerment,
like th
for SGMII interfaces, there can be 0 value
written on MAC registers.
This patch set the random MAC address for those
interfaces.
Signed-off-by: Gagandeep Singh
---
drivers/net/enetc/enetc_ethdev.c | 33 +++-
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git
enetc BD rings should be aligned to 128
instead of RTE_CACHE_LINE_SIZE.
Signed-off-by: Gagandeep Singh
---
drivers/net/enetc/base/enetc_hw.h | 3 +++
drivers/net/enetc/enetc_ethdev.c | 8
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/net/enetc/base/enetc_hw.h
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