# Is PPC and other ARM SoC has formula (B) to compute DRAM channel
distribution ? or
Is it specific to x86? That would define where the hooks needs to added to have
proper fix.
The Power 9 chip has eight memory channels, each with a dedicated memory
controller unit (MCU). The MCUs can be conf
tel.com; konstantin.anan...@intel.com;
> hemant.agra...@nxp.com; Shahaf Shuler ;
> Honnappa Nagarahalli ;
> vikto...@rehivetech.com; anatoly.bura...@intel.com; Steve Capper
> ; Ola Liljedahl ; nd
>
> Subject: Re: [dpdk-dev] Mbuf memory alignment constraints for
> (micro)architecture
Hi Jerin,
> -Original Message-
> From: Jerin Jacob Kollanukkaran
> Sent: Thursday, October 31, 2019 2:02 AM
> To: dev@dpdk.org
> Cc: Olivier Matz ; Andrew Rybchenko
> ; David Christensen ;
> bruce.richard...@intel.com; konstantin.anan...@intel.com;
> hemant.agra...@nxp.com; Shahaf Shuler
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