On Thu, Sep 07, 2017 at 02:26:49PM +0530, santosh wrote:
>
> On Thursday 07 September 2017 02:00 PM, Olivier MATZ wrote:
> > On Wed, Sep 06, 2017 at 04:58:34PM +0530, Santosh Shukla wrote:
> >> HW pool manager e.g. Octeontx SoC demands s/w to program start and end
> >> address of pool. Currently,
On Thursday 07 September 2017 02:00 PM, Olivier MATZ wrote:
> On Wed, Sep 06, 2017 at 04:58:34PM +0530, Santosh Shukla wrote:
>> HW pool manager e.g. Octeontx SoC demands s/w to program start and end
>> address of pool. Currently, there is no such handle in external mempool.
>> Introducing rte_mem
On Wed, Sep 06, 2017 at 04:58:34PM +0530, Santosh Shukla wrote:
> HW pool manager e.g. Octeontx SoC demands s/w to program start and end
> address of pool. Currently, there is no such handle in external mempool.
> Introducing rte_mempool_update_range handle which will let HW(pool
> manager) to know
HW pool manager e.g. Octeontx SoC demands s/w to program start and end
address of pool. Currently, there is no such handle in external mempool.
Introducing rte_mempool_update_range handle which will let HW(pool
manager) to know when common layer selects hugepage:
For each hugepage - update its star
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