Hi Matan,
On Tue, Oct 31, 2017 at 11:35:29AM +, Matan Azrad wrote:
> > -Original Message-
> > From: Adrien Mazarguil [mailto:adrien.mazarg...@6wind.com]
> > Sent: Tuesday, October 31, 2017 12:17 PM
> > To: Matan Azrad
> > Cc: dev@dpdk.org; Ophir Munk
> > Subject: Re: [PATCH v3 6/7]
Hi Adrien
> -Original Message-
> From: Adrien Mazarguil [mailto:adrien.mazarg...@6wind.com]
> Sent: Tuesday, October 31, 2017 12:17 PM
> To: Matan Azrad
> Cc: dev@dpdk.org; Ophir Munk
> Subject: Re: [PATCH v3 6/7] net/mlx4: mitigate Tx path memory barriers
>
> Hi Matan,
>
> On Mon, Oct
Hi Matan,
On Mon, Oct 30, 2017 at 07:47:20PM +, Matan Azrad wrote:
> Hi Adrien
>
> > -Original Message-
> > From: Adrien Mazarguil [mailto:adrien.mazarg...@6wind.com]
> > Sent: Monday, October 30, 2017 4:24 PM
> > To: Matan Azrad
> > Cc: dev@dpdk.org; Ophir Munk
> > Subject: Re: [PA
Hi Adrien
> -Original Message-
> From: Adrien Mazarguil [mailto:adrien.mazarg...@6wind.com]
> Sent: Monday, October 30, 2017 4:24 PM
> To: Matan Azrad
> Cc: dev@dpdk.org; Ophir Munk
> Subject: Re: [PATCH v3 6/7] net/mlx4: mitigate Tx path memory barriers
>
> On Mon, Oct 30, 2017 at 10:0
On Mon, Oct 30, 2017 at 10:07:28AM +, Matan Azrad wrote:
> Replace most of the memory barriers by compiler barriers since they are
> all targeted to the DRAM; This improves code efficiency for systems
> which force store order between different addresses.
>
> Only the doorbell record store sho
Replace most of the memory barriers by compiler barriers since they are
all targeted to the DRAM; This improves code efficiency for systems
which force store order between different addresses.
Only the doorbell record store should be protected by memory barrier
since it is targeted to the PCI memo
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