On Fri, Mar 6, 2020 at 10:35 AM Gavin Hu wrote:
>
> To keep ordering of mixed accesses, rte_cio is sufficient.
> The rte_io barrier inside the I40E_PCI_REG_WRITE is overkill.[1]
>
> This patch fixes by replacing with just sufficient barriers in the
> normal PMD and vPMD.
>
> It showed 7% performan
To keep ordering of mixed accesses, rte_cio is sufficient.
The rte_io barrier inside the I40E_PCI_REG_WRITE is overkill.[1]
This patch fixes by replacing with just sufficient barriers in the
normal PMD and vPMD.
It showed 7% performance uplift on ThunderX2 and 4% on Arm N1SDP.
The test case is th
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