On Wed, Mar 01, 2017 at 04:49:56PM +0530, Jerin Jacob wrote:
> On Wed, Mar 01, 2017 at 12:06:33PM +0100, Olivier Matz wrote:
> > On Wed, 1 Mar 2017 10:42:58 +, Bruce Richardson
> > wrote:
> > > On Wed, Mar 01, 2017 at 11:17:53AM +0100, Olivier Matz wrote:
> > > > On Wed, 1 Mar 2017 09:47:03 +
On Wed, Mar 01, 2017 at 12:06:33PM +0100, Olivier Matz wrote:
> On Wed, 1 Mar 2017 10:42:58 +, Bruce Richardson
> wrote:
> > On Wed, Mar 01, 2017 at 11:17:53AM +0100, Olivier Matz wrote:
> > > On Wed, 1 Mar 2017 09:47:03 +, Bruce Richardson
> > > wrote:
> > > > So given that there is n
On Wed, 1 Mar 2017 10:42:58 +, Bruce Richardson
wrote:
> On Wed, Mar 01, 2017 at 11:17:53AM +0100, Olivier Matz wrote:
> > On Wed, 1 Mar 2017 09:47:03 +, Bruce Richardson
> > wrote:
> > > So given that there is not much difference here, is the MIN_SIZE i.e.
> > > forced 64B, your prefe
On Wed, Mar 01, 2017 at 11:17:53AM +0100, Olivier Matz wrote:
> Hi Bruce,
>
> On Wed, 1 Mar 2017 09:47:03 +, Bruce Richardson
> wrote:
> > On Tue, Feb 28, 2017 at 11:24:25PM +0530, Jerin Jacob wrote:
> > > On Tue, Feb 28, 2017 at 01:52:26PM +, Bruce Richardson wrote:
> > > > On Tue, Feb
Hi Bruce,
On Wed, 1 Mar 2017 09:47:03 +, Bruce Richardson
wrote:
> On Tue, Feb 28, 2017 at 11:24:25PM +0530, Jerin Jacob wrote:
> > On Tue, Feb 28, 2017 at 01:52:26PM +, Bruce Richardson wrote:
> > > On Tue, Feb 28, 2017 at 05:38:34PM +0530, Jerin Jacob wrote:
> > > > On Tue, Feb 28,
On Tue, Feb 28, 2017 at 11:24:25PM +0530, Jerin Jacob wrote:
> On Tue, Feb 28, 2017 at 01:52:26PM +, Bruce Richardson wrote:
> > On Tue, Feb 28, 2017 at 05:38:34PM +0530, Jerin Jacob wrote:
> > > On Tue, Feb 28, 2017 at 11:57:03AM +, Bruce Richardson wrote:
> > > > On Tue, Feb 28, 2017 at 0
On Tue, Feb 28, 2017 at 01:52:26PM +, Bruce Richardson wrote:
> On Tue, Feb 28, 2017 at 05:38:34PM +0530, Jerin Jacob wrote:
> > On Tue, Feb 28, 2017 at 11:57:03AM +, Bruce Richardson wrote:
> > > On Tue, Feb 28, 2017 at 05:05:13PM +0530, Jerin Jacob wrote:
> > > > On Thu, Feb 23, 2017 at 0
On Tue, Feb 28, 2017 at 05:38:34PM +0530, Jerin Jacob wrote:
> On Tue, Feb 28, 2017 at 11:57:03AM +, Bruce Richardson wrote:
> > On Tue, Feb 28, 2017 at 05:05:13PM +0530, Jerin Jacob wrote:
> > > On Thu, Feb 23, 2017 at 05:23:54PM +, Bruce Richardson wrote:
> > > > Users compiling DPDK shou
On Tue, Feb 28, 2017 at 11:57:03AM +, Bruce Richardson wrote:
> On Tue, Feb 28, 2017 at 05:05:13PM +0530, Jerin Jacob wrote:
> > On Thu, Feb 23, 2017 at 05:23:54PM +, Bruce Richardson wrote:
> > > Users compiling DPDK should not need to know or care about the arrangement
> > > of cachelines
On Tue, Feb 28, 2017 at 05:05:13PM +0530, Jerin Jacob wrote:
> On Thu, Feb 23, 2017 at 05:23:54PM +, Bruce Richardson wrote:
> > Users compiling DPDK should not need to know or care about the arrangement
> > of cachelines in the rte_ring structure. Therefore just remove the build
> > option and
On Thu, Feb 23, 2017 at 05:23:54PM +, Bruce Richardson wrote:
> Users compiling DPDK should not need to know or care about the arrangement
> of cachelines in the rte_ring structure. Therefore just remove the build
> option and set the structures to be always split. For improved
> performance us
Users compiling DPDK should not need to know or care about the arrangement
of cachelines in the rte_ring structure. Therefore just remove the build
option and set the structures to be always split. For improved
performance use 128B rather than 64B alignment since it stops the producer
and consumer
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