-#define ITER_MAX 0x1
+#define ITER_MAX 0x100
This is a revert of a change done in patch 3.
I'll fix and resubmit.
@@ -92,12 +92,19 @@ struct lcore_plock_test {
other = self ^ 1;
l->flag[self] = 1;
+#ifdef RTE_ARCH_PPC_64
+ rte_smp_wmb();
+#endi
Hi,
01/05/2019 00:33, David Christensen:
> The memory barrier test fails on IBM Power 9 systems. Add additional
> barriers to accommodate the weakly ordered model used on Power CPUs.
>
> Signed-off-by: David Christensen
[...]
> --- a/app/test/test_barrier.c
> +++ b/app/test/test_barrier.c
> @@
The memory barrier test fails on IBM Power 9 systems. Add additional
barriers to accommodate the weakly ordered model used on Power CPUs.
Signed-off-by: David Christensen
---
app/test/test_barrier.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/app/test/test_barrie
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