Hi, Slava
Thank you for taking the time to review this patch.
I agree with you. The current design is very comprehensive. I will abandon this
patch.
Thanks,
Phil Yang
> -Original Message-
> From: Phil Yang (Arm Technology China)
> Sent: Monday, September 9, 2019 13:12
> To: Slava Ovsiienko ; Yongseok Koh
> ; Matan Azrad ; Nélio
> Laranjeiro ; dev@dpdk.org
> Cc: Thomas Monjalon ; jer...@marvell.com;
> Honnappa Nagarahalli ; Gavin Hu (Arm
> Technology Chi
> -Original Message-
> From: Slava Ovsiienko
> Sent: Friday, September 6, 2019 8:27 PM
> To: Phil Yang (Arm Technology China) ;
> ys...@mellanox.com; Matan Azrad ; Nélio
> Laranjeiro ; dev@dpdk.org
> Cc: tho...@monjalon.net; jer...@marvell.com; Honnappa Nagarahalli
> ; Gavin Hu (Arm Techno
Hi, Phil
Thanks for explanations, please, see below.
> -Original Message-
> From: Phil Yang (Arm Technology China)
> Sent: Friday, September 6, 2019 10:20
> To: Slava Ovsiienko ; Yongseok Koh
> ; Matan Azrad ; Nélio
> Laranjeiro ; dev@dpdk.org
> Cc: Thomas Monjalon ; jer...@marvell.com;
Hi, Slava
Thanks for your comments.
> -Original Message-
> From: Slava Ovsiienko
> Sent: Thursday, September 5, 2019 8:12 PM
> To: Phil Yang (Arm Technology China) ;
> ys...@mellanox.com; Matan Azrad ; Nélio
> Laranjeiro ; dev@dpdk.org
> Cc: tho...@monjalon.net; jer...@marvell.com; Honn
Hi, Phil
This point is in datapath and performance is very critical.
The rte_cio_wmb() may take a lot of CPU cycles, waiting till all previous
writes become
visible for all external (relating to core) agents. The Tx CQE doorbelling does
not need
any writes to other locations to be completed, the
For the weaker memory model processors, the compiler barrier is not
sufficient to guarantee the coherent memory update be observed by
I/O device. It needs the coherent I/O memory barrier to enforce the
ordering of Tx completion queue doorbell operation.
Fixes: da1df1ccabad ("net/mlx5: fix completi
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