Re: [PATCH v9 14/21] net/ntnic: add clock profile for the NT200A0X smartNIC

On 7/16/2024 1:02 PM, Serhii Iliushyk wrote: > diff --git > a/drivers/net/ntnic/nthw/core/nt200a0x/clock_profiles/nthw_fpga_clk9563.c > b/drivers/net/ntnic/nthw/core/nt200a0x/clock_profiles/nthw_fpga_clk9563.c > new file mode 100644 > index 00..a957581bf3 > --- /dev/null > +++ b/drivers/n

[PATCH v9 14/21] net/ntnic: add clock profile for the NT200A0X smartNIC

Because the ntnic hardware supports multiple different FPGAs with different pipelines and port speeds, the clock profile is not hardcoded into the product, and need to be initialized from software. The clock profile itself is an array of integers that was generated by Silicon Labs ClockBuilder. S