> From: Honnappa Nagarahalli [mailto:honnappa.nagaraha...@arm.com]
> Sent: Wednesday, 22 March 2023 14.42
>
> > From: Morten Brørup
> > Sent: Wednesday, March 22, 2023 7:57 AM
> >
> > > From: Feifei Wang [mailto:feifei.wa...@arm.com]
> > > Sent: Wednesday, 4 January 2023 08.31
> > >
> > > Current
i
> Subject: RE: [PATCH v3 0/3] Direct re-arming of buffers on receive side
>
> > From: Feifei Wang [mailto:feifei.wa...@arm.com]
> > Sent: Wednesday, 4 January 2023 08.31
> >
> > Currently, the transmit side frees the buffers into the lcore cache
> > and
> From: Feifei Wang [mailto:feifei.wa...@arm.com]
> Sent: Wednesday, 4 January 2023 08.31
>
> Currently, the transmit side frees the buffers into the lcore cache and
> the receive side allocates buffers from the lcore cache. The transmit
> side typically frees 32 buffers resulting in 32*8=256B of
That's all right. Thanks very much for your attention~
> -邮件原件-
> 发件人: Konstantin Ananyev
> 发送时间: Wednesday, February 1, 2023 9:11 AM
> 收件人: Feifei Wang
> 抄送: dev@dpdk.org; nd
> 主题: Re: 回复: [PATCH v3 0/3] Direct re-arming of buffers on receive side
>
Hi Feifei,
+ping konstantin，
Would you please give some comments for this patch series?
Thanks very much.
Sure, will have a look in next few days.
Apologies for the delay.
+ping konstantin，
Would you please give some comments for this patch series?
Thanks very much.
Best Regards
Feifei
Currently, the transmit side frees the buffers into the lcore cache and
the receive side allocates buffers from the lcore cache. The transmit
side typically frees 32 buffers resulting in 32*8=256B of stores to
lcore cache. The receive side allocates 32 buffers and stores them in
the receive side so
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