Replacing myself as Crypto Perf App maintainer with Brian Dooley.
Signed-off-by: Ciara Power
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7726e9e7a9..4e4197e178 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1825,7 +1825,7
Replacing myself as Telemetry maintainer with Bruce Richardson.
Signed-off-by: Ciara Power
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7abb3aee49..7726e9e7a9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1739,7 +1739,7
ned-off-by: Ciara Power
---
lib/cryptodev/rte_cryptodev.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/lib/cryptodev/rte_cryptodev.h b/lib/cryptodev/rte_cryptodev.h
index 00ba6a234a..357d4bcf9c 100644
--- a/lib/cryptodev/rte_cryptodev.h
+++ b/lib/cryptodev/rte_c
When using RTE_ENABLE_ASSERT and debug mode, an undefined
macro error appeared for ICP_QAT_FW_SYM_COMM_ADDR_SGL.
This was not being defined, but is now added to the header file.
Bugzilla ID: 1395
Fixes: e9271821e489 ("common/qat: support GEN LCE device")
Signed-off-by: Ciara Powe
: Nishikant Nayak
Signed-off-by: Ciara Power
Acked-by: Arkadiusz Kusztal
---
v7:
- Added second developer to signed-off for v7 fixes.
- Utilised 100 char line limit.
- Moved NULL capability check earlier in test function.
v2:
- Removed unused code.
- Added one new unit test, AAD
From: Nishikant Nayak
This patch handles the changes required for updating the common
header fields specific to GEN LCE, Also added/updated of the response
processing APIs based on GEN LCE requirement.
Signed-off-by: Nishikant Nayak
Signed-off-by: Ciara Power
Acked-by: Arkadiusz Kusztal
: Ciara Power
Acked-by: Arkadiusz Kusztal
---
v7:
- Squashed patch 1 + 2 together.
- Updated commit message.
- Added new signed off to cover changes made by
second developer in v7.
- Fixed copyright year for new files.
- Utilised 100 char line limit.
v6:
- Removed
This patchset adds a new QAT LCE device.
The device currently only supports symmetric crypto,
and only the AES-GCM algorithm.
v8: Rebased on latest next-crypto-for-main.
v7:
- Squashed patch 1 and 2.
- Fixed formatting to leverage 100 char line limit.
- Removed unnecessary whitespace and ind
: Nishikant Nayak
Signed-off-by: Ciara Power
Acked-by: Arkadiusz Kusztal
---
v7:
- Added second developer to signed-off for v7 fixes.
- Utilised 100 char line limit.
- Moved NULL capability check earlier in test function.
v2:
- Removed unused code.
- Added one new unit test, AAD
From: Nishikant Nayak
This patch handles the changes required for updating the common
header fields specific to GEN LCE, Also added/updated of the response
processing APIs based on GEN LCE requirement.
Signed-off-by: Nishikant Nayak
Signed-off-by: Ciara Power
Acked-by: Arkadiusz Kusztal
: Ciara Power
Acked-by: Arkadiusz Kusztal
---
v7:
- Squashed patch 1 + 2 together.
- Updated commit message.
- Added new signed off to cover changes made by
second developer in v7.
- Fixed copyright year for new files.
- Utilised 100 char line limit.
v6:
- Removed
This patchset adds a new QAT LCE device.
The device currently only supports symmetric crypto,
and only the AES-GCM algorithm.
v7:
- Squashed patch 1 and 2.
- Fixed formatting to leverage 100 char line limit.
- Removed unnecessary whitespace and indent changes.
- Fixed copyright year typo o
.
Symmetric, asymmetric and compression services are enabled.
Signed-off-by: Ciara Power
Acked-by: Kai Ji
---
v3:
- Fixed copyright tag in new files to 2024.
- Removed v2 changes in notes of commit, this patch was new in v2.
---
doc/guides/cryptodevs/qat.rst| 4 +
doc/guides
The new QAT GEN3 device uses new macros for CMAC values, rather than
using XCBC_MAC ones.
The wireless slice handles CMAC in the new gen3 device, and no key
precomputes are required by SW.
Signed-off-by: Ciara Power
Acked-by: Kai Ji
---
drivers/common/qat/qat_adf/icp_qat_hw.h | 4
capability for the
device.
The device supports 24 bytes iv for ZUC 256, with iv[20]
being ignored in register.
For 25 byte iv, compress this into 23 bytes.
Signed-off-by: Ciara Power
Acked-by: Kai Ji
---
v2:
- Fixed setting extended protocol flag bit position.
- Added slice map check for ZUC256
, asymmetric and compression services are enabled.
Signed-off-by: Ciara Power
Acked-by: Kai Ji
---
v2: Added documentation updates.
---
doc/guides/compressdevs/qat_comp.rst | 1 +
doc/guides/cryptodevs/qat.rst| 2 ++
doc/guides/rel_notes/release_24_03.rst | 4
.
- Added check for ZUC-256 wireless slice in slice map.
Ciara Power (4):
common/qat: add new gen3 device
common/qat: add zuc256 wireless slice for gen3
common/qat: add new gen3 CMAC macros
common/qat: add gen5 device
doc/guides/compressdevs/qat_comp.rst | 1 +
doc/guides
.
Symmetric, asymmetric and compression services are enabled.
Signed-off-by: Ciara Power
---
v2:
- Fixed setting extended protocol flag bit position.
- Added slice map check for ZUC256 wireless slice.
- Fixed IV modification for ZUC256 in raw datapath.
- Added increment size for ZUC256
The new QAT GEN3 device uses new macros for CMAC values, rather than
using XCBC_MAC ones.
The wireless slice handles CMAC in the new gen3 device, and no key
precomputes are required by SW.
Signed-off-by: Ciara Power
---
drivers/common/qat/qat_adf/icp_qat_hw.h | 4 +++-
drivers/crypto/qat
capability for the
device.
The device supports 24 bytes iv for ZUC 256, with iv[20]
being ignored in register.
For 25 byte iv, compress this into 23 bytes.
Signed-off-by: Ciara Power
---
v2:
- Fixed setting extended protocol flag bit position.
- Added slice map check for ZUC256 wireless slice
, asymmetric and compression services are enabled.
Signed-off-by: Ciara Power
---
v2: Added documentation updates.
---
doc/guides/compressdevs/qat_comp.rst | 1 +
doc/guides/cryptodevs/qat.rst| 2 ++
doc/guides/rel_notes/release_24_03.rst | 4
drivers/common
.
Ciara Power (4):
common/qat: add new gen3 device
common/qat: add zuc256 wireless slice for gen3
common/qat: add new gen3 CMAC macros
common/qat: add gen5 device
doc/guides/compressdevs/qat_comp.rst | 1 +
doc/guides/cryptodevs/qat.rst| 6 +
doc/guides
Currently only symmetric crypto has been added for the new gen3 device,
adding a check to disable asym and comp PMDs for this device.
Signed-off-by: Ciara Power
---
drivers/compress/qat/qat_comp_pmd.c | 3 ++-
drivers/crypto/qat/qat_asym.c | 3 ++-
2 files changed, 4 insertions(+), 2
The new QAT GEN3 device uses new macros for CMAC values, rather than
using XCBC_MAC ones.
The wireless slice handles CMAC in the new gen3 device, and no key
precomputes are required by SW.
Signed-off-by: Ciara Power
---
drivers/common/qat/qat_adf/icp_qat_hw.h | 4 +++-
drivers/crypto/qat
capability for the
device.
The device supports 24 bytes iv for ZUC 256, with iv[20]
being ignored in register.
For 25 byte iv, compress this into 23 bytes.
Signed-off-by: Ciara Power
---
drivers/common/qat/qat_adf/icp_qat_fw.h | 3 +-
drivers/common/qat/qat_adf/icp_qat_fw_la.h | 24
moved to wireless slice (SNOW3G, ZUC, AES-CMAC).
This patchset covers Symmetric crypto, so a check has been added for
Asymmetric and Compression PMDs to skip for this gen3 device only.
Documentation will be updated in a subsequent version of the patchset.
Ciara Power (4):
crypto/qat: add new
-by: Ciara Power
---
drivers/common/qat/qat_device.c | 13 +
drivers/common/qat/qat_device.h | 2 ++
drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c | 11 +++
3 files changed, 26 insertions(+)
diff --git a/drivers/common/qat/qat_device.c b/drivers/common
: 9593d83e5d88 ("crypto/ipsec_mb: fix aesni_mb multi-process session ID")
Cc: sta...@dpdk.org
Signed-off-by: Ciara Power
---
drivers/crypto/ipsec_mb/pmd_aesni_mb.c | 22 ++
1 file changed, 18 insertions(+), 4 deletions(-)
diff --git a/drivers/crypto/ipsec_mb/pmd_aes
: 9593d83e5d88 ("crypto/ipsec_mb: fix aesni_mb multi-process session ID")
Cc: sta...@dpdk.org
Signed-off-by: Ciara Power
---
drivers/crypto/ipsec_mb/pmd_aesni_mb.c | 22 ++
1 file changed, 18 insertions(+), 4 deletions(-)
diff --git a/drivers/crypto/ipsec_mb/pmd_aes
the legacy capabilities list is
moved to the top of the loop, so it is detected when the last legacy
element is SM and no SM slice exists.
Fixes: cffb726b7797 ("crypto/qat: enable insecure algorithms")
Cc: sta...@dpdk.org
Signed-off-by: Ciara Power
---
v2: updating sender email
---
driv
("crypto/openssl: add DH and DSA asym operations")
Fixes: d7bd42f6db19 ("crypto/openssl: update RSA routine with 3.0 EVP API")
Fixes: ad149f93093e ("crypto/openssl: fix memory leaks in asym ops")
Cc: kai...@intel.com
Cc: gmuthukri...@marvell.com
Cc: sunila.s...@caviumnetw
("crypto/openssl: add DH and DSA asym operations")
Fixes: d7bd42f6db19 ("crypto/openssl: update RSA routine with 3.0 EVP API")
Fixes: ad149f93093e ("crypto/openssl: fix memory leaks in asym ops")
Cc: kai...@intel.com
Cc: gmuthukri...@marvell.com
Cc: sunila.s...@caviumnetw
11f ("crypto/openssl: support asymmetric SM2")
Fixes: ac42813a0a7c ("crypto/openssl: add DH and DSA asym operations")
Fixes: d7bd42f6db19 ("crypto/openssl: update RSA routine with 3.0 EVP API")
Cc: kai...@intel.com
Cc: gmuthukri...@marvell.com
Cc: sunila.s...@caviumnetworks.c
code so it does not depend on openssl at all.
Fixes: ca0ba0e48129 ("crypto/qat: default to IPsec MB for computations")
Cc: brian.doo...@intel.com
Cc: sta...@dpdk.org
Signed-off-by: Ciara Power
---
drivers/crypto/qat/dev/qat_crypto_pmd_gens.h | 2 ++
drivers/crypto/qat
From: Arkadiusz Kusztal
Some of the API comments incorrectly limited the usage of symmetric
crypto fields to block ciphers.
Signed-off-by: Arkadiusz Kusztal
Signed-off-by: Ciara Power
---
lib/cryptodev/rte_crypto_sym.h | 19 +--
1 file changed, 5 insertions(+), 14 deletions
expected, and the digest
is placed to the side, as it won't be used anyway.
This fix was previously added for the main QAT code path, but it also
needs to be included for the raw API code path.
Fixes: db0e952a5c01 ("crypto/qat: add NULL capability")
Cc: sta...@dpdk.org
Signed-off-
This commit enables QAT 2.0c devices in the
Intel QuickAssist Technology PMD.
These are 4th Generation QAT, 402xx devices.
Signed-off-by: Ciara Power
---
v2:
- Fixed kernel module.
- Modified commit to align naming of new QAT device.
---
doc/guides/cryptodevs/qat.rst | 4
doc
This commit enables QAT 2.0c devices in the
Intel QuickAssist Technology PMD.
Signed-off-by: Ciara Power
---
doc/guides/cryptodevs/qat.rst | 4
doc/guides/rel_notes/release_23_11.rst | 3 +++
drivers/common/qat/qat_device.c| 4
3 files changed, 11 insertions(+)
diff
check range of socket id")
Cc: bruce.richard...@intel.com
Cc: olivier.m...@6wind.com
Cc: sta...@dpdk.org
Signed-off-by: Ciara Power
Acked-by: Kai Ji
---
v2: check if socket ID equals SOCKET_ID_ANY
---
app/test-crypto-perf/main.c | 15 +--
1 file changed, 9 insertions(+), 6 deleti
Updated AESNI MB and AESNI GCM, KASUMI, ZUC, SNOW3G
and CHACHA20_POLY1305 PMD documentation guides
with information about the latest Intel IPsec Multi-buffer
library supported.
Signed-off-by: Ciara Power
---
doc/guides/cryptodevs/aesni_gcm.rst | 6 +++---
doc/guides/cryptodevs
Following the deprecation of insecure algorithms in QAT,
SM4-ECB should be included as legacy, to be disabled by default.
Fixes: cffb726b7797 ("crypto/qat: enable insecure algorithms")
Signed-off-by: Ciara Power
---
drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c | 6 +++---
1 file
type to int fixes the issue, as it now takes the
correct -1 value.
Fixes: 7dcd73e37965 ("drivers/bus: set device NUMA node to unknown by default")
Cc: olivier.m...@6wind.com
Cc: sta...@dpdk.org
Signed-off-by: Ciara Power
Acked-by: Morten Brørup
Acked-by: Kai Ji
---
v2: Added cc for stab
rg
Signed-off-by: Ciara Power
---
app/test-crypto-perf/main.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/app/test-crypto-perf/main.c b/app/test-crypto-perf/main.c
index af5bd0d23b..b74e7ba118 100644
--- a/app/test-crypto-perf/main.c
+++ b/app/test-crypto-perf/main.c
@@ -651,6 +651,
ec_mb: use burst API in AESNI")
Cc: marcel.d.co...@intel.com
Signed-off-by: Ciara Power
Acked-by: Kai Ji
---
v2: fixed typo in commit
---
drivers/crypto/ipsec_mb/pmd_aesni_mb.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/crypto/ipsec_mb/pmd_aesni_mb.c
ec_mb: use burst API in AESNI")
Cc: marcel.d.co...@intel.com
Signed-off-by: Ciara Power
---
drivers/crypto/ipsec_mb/pmd_aesni_mb.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/crypto/ipsec_mb/pmd_aesni_mb.c
b/drivers/crypto/ipsec_mb/pmd_aesni_mb.c
index
template session to the job again.
Fixes: 0fb4834e00af ("crypto/ipsec_mb: set and use session ID")
Cc: pablo.de.lara.gua...@intel.com
Signed-off-by: Ciara Power
---
drivers/crypto/ipsec_mb/pmd_aesni_mb.c | 8 +++-
drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h | 2 ++
2 files
type to int fixes the issue, as it now takes the
correct -1 value.
Fixes: 7dcd73e37965 ("drivers/bus: set device NUMA node to unknown by default")
Cc: olivier.m...@6wind.com
Signed-off-by: Ciara Power
---
lib/cryptodev/cryptodev_pmd.h | 2 +-
1 file changed, 1 insertion(+), 1 deletio
expected, and the digest
is placed to the side, as it won't be used anyway.
Fixes: db0e952a5c01 ("crypto/qat: add NULL capability")
Signed-off-by: Ciara Power
---
v2: added fixes line as this was a bug
---
drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c | 2 +-
drivers
expected, and the digest
is placed to the side, as it won't be used anyway.
Signed-off-by: Ciara Power
---
drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c | 2 +-
drivers/crypto/qat/dev/qat_crypto_pmd_gens.h | 18 ++
drivers/crypto/qat/dev/qat_sym_pmd_gen1.c| 4 ++--
dr
c SM2")
Cc: gmuthukri...@marvell.com
Signed-off-by: Ciara Power
---
drivers/crypto/openssl/rte_openssl_pmd_ops.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/crypto/openssl/rte_openssl_pmd_ops.c
b/drivers/crypto/openssl/rte_openssl_pmd_ops.c
index fe38e4ebd8..9497da41ef 10
framework")
Cc: sta...@dpdk.org
Signed-off-by: Pablo de Lara
Signed-off-by: Ciara Power
---
v2: fixed indents
---
drivers/crypto/ipsec_mb/ipsec_mb_ops.c | 17 +
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/drivers/crypto/ipsec_mb/ipsec_mb_ops.c
b/drivers/
framework")
Cc: sta...@dpdk.org
Signed-off-by: Pablo de Lara
Signed-off-by: Ciara Power
---
drivers/crypto/ipsec_mb/ipsec_mb_ops.c | 17 +
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/drivers/crypto/ipsec_mb/ipsec_mb_ops.c
b/drivers/crypto/ipsec_mb/ipsec
illed again.
Signed-off-by: Pablo de Lara
Signed-off-by: Ciara Power
---
drivers/crypto/ipsec_mb/pmd_aesni_mb.c | 22 -
drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h | 2 ++
2 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/drivers/crypto/ipsec_mb/pmd_aesni
From: Pablo de Lara
linear_sgl buffer only needs to be freed
if it was allocated previously.
Signed-off-by: Pablo de Lara
---
drivers/crypto/ipsec_mb/pmd_aesni_mb.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/crypto/ipsec_mb/pmd_aesni_mb.c
b/drivers/crypto
From: Pablo de Lara
Use a separate code path when dealing with AES-GCM.
Signed-off-by: Pablo de Lara
Signed-off-by: Ciara Power
---
drivers/crypto/ipsec_mb/pmd_aesni_mb.c | 88 +++---
1 file changed, 79 insertions(+), 9 deletions(-)
diff --git a/drivers/crypto/ipsec_mb
-by: Ciara Power
---
drivers/crypto/ipsec_mb/pmd_aesni_mb.c | 403
drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h | 20 +-
2 files changed, 159 insertions(+), 264 deletions(-)
diff --git a/drivers/crypto/ipsec_mb/pmd_aesni_mb.c
b/drivers/crypto/ipsec_mb/pmd_aesni_mb.c
From: Pablo de Lara
Cipher direction, cipher mode and hash algorithm are
duplicated in crypto session.
Signed-off-by: Pablo de Lara
---
drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h
b/drivers/crypt
: Ciara Power
---
drivers/crypto/ipsec_mb/pmd_aesni_mb.c | 187 +++-
drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h | 7 +
2 files changed, 153 insertions(+), 41 deletions(-)
diff --git a/drivers/crypto/ipsec_mb/pmd_aesni_mb.c
b/drivers/crypto/ipsec_mb/pmd_aesni_mb.c
index
From: Marcel Cornu
Use new ipsec_mb burst API in dequeue burst function,
when ipsec_mb version is v1.3 or newer.
Signed-off-by: Marcel Cornu
Signed-off-by: Pablo de Lara
Signed-off-by: Ciara Power
---
v2: moved some functions inside ifdef as they are only used when
IPSec_MB version is
From: Pablo de Lara
AES-GMAC can be done with auth-only enums
IMB_AES_GMAC_128/192/256, which allows another cipher
algorithm to be used, instead of being part of AES-GCM.
Signed-off-by: Pablo de Lara
Signed-off-by: Ciara Power
---
drivers/crypto/ipsec_mb/pmd_aesni_mb.c | 104
This patchset adds some optimisations for AESNI_MB PMD, many based on
features that are available in intel-ipsec-mb v1.3 and future release v1.4.
v2: moved some functions inside ifdef as they are only used when
IPSec_MB version is 1.2 or lower.
Marcel Cornu (1):
crypto/ipsec_mb: use burst A
enssl: update DSA routine with 3.0 EVP API")
Cc: kai...@intel.com
Cc: sta...@dpdk.org
Signed-off-by: Saoirse O'Donovan
Signed-off-by: Ciara Power
---
drivers/crypto/openssl/rte_openssl_pmd.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/crypto/ope
illed again.
Signed-off-by: Pablo de Lara
Signed-off-by: Ciara Power
---
drivers/crypto/ipsec_mb/pmd_aesni_mb.c | 22 -
drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h | 2 ++
2 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/drivers/crypto/ipsec_mb/pmd_aesni
From: Pablo de Lara
linear_sgl buffer only needs to be freed
if it was allocated previously.
Signed-off-by: Pablo de Lara
---
drivers/crypto/ipsec_mb/pmd_aesni_mb.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/crypto/ipsec_mb/pmd_aesni_mb.c
b/drivers/crypto
From: Pablo de Lara
Use a separate code path when dealing with AES-GCM.
Signed-off-by: Pablo de Lara
Signed-off-by: Ciara Power
---
drivers/crypto/ipsec_mb/pmd_aesni_mb.c | 88 +++---
1 file changed, 79 insertions(+), 9 deletions(-)
diff --git a/drivers/crypto/ipsec_mb
-by: Ciara Power
---
drivers/crypto/ipsec_mb/pmd_aesni_mb.c | 403
drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h | 20 +-
2 files changed, 159 insertions(+), 264 deletions(-)
diff --git a/drivers/crypto/ipsec_mb/pmd_aesni_mb.c
b/drivers/crypto/ipsec_mb/pmd_aesni_mb.c
From: Pablo de Lara
Cipher direction, cipher mode and hash algorithm are
duplicated in crypto session.
Signed-off-by: Pablo de Lara
---
drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h
b/drivers/crypt
: Ciara Power
---
drivers/crypto/ipsec_mb/pmd_aesni_mb.c | 187 +++-
drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h | 7 +
2 files changed, 153 insertions(+), 41 deletions(-)
diff --git a/drivers/crypto/ipsec_mb/pmd_aesni_mb.c
b/drivers/crypto/ipsec_mb/pmd_aesni_mb.c
index
From: Pablo de Lara
AES-GMAC can be done with auth-only enums
IMB_AES_GMAC_128/192/256, which allows another cipher
algorithm to be used, instead of being part of AES-GCM.
Signed-off-by: Pablo de Lara
Signed-off-by: Ciara Power
---
drivers/crypto/ipsec_mb/pmd_aesni_mb.c | 104
From: Marcel Cornu
Use new ipsec_mb burst API in dequeue burst function,
when ipsec_mb version is v1.3 or newer.
Signed-off-by: Marcel Cornu
Signed-off-by: Pablo de Lara
Signed-off-by: Ciara Power
---
drivers/crypto/ipsec_mb/pmd_aesni_mb.c | 133 -
1 file changed
This patchset adds some optimisations for AESNI_MB PMD, many based on
features that are available in intel-ipsec-mb v1.3 and future release v1.4.
Marcel Cornu (1):
crypto/ipsec_mb: use burst API in aesni_mb
Pablo de Lara (7):
crypto/ipsec_mb: use GMAC dedicated algorithms
crypto/ipsec_mb: u
vdev driver")
Cc: fanzhang@gmail.com
Cc: sta...@dpdk.org
Signed-off-by: Ciara Power
---
drivers/crypto/scheduler/scheduler_pmd.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/crypto/scheduler/scheduler_pmd.c
b/drivers/crypto/scheduler/scheduler_pmd.c
index
e i value, which represents the number
of cvecs available.
If i is 0, then no need to increment as the current cvec is the last one.
Fixes: a815a04cea05 ("crypto/qat: support symmetric build op request")
Cc: kai...@intel.com
Cc: sta...@dpdk.org
Signed-off-by: Ciara Power
---
drivers/c
From: Arkadiusz Kusztal
Individual variables are needed for tracking the remaining data for
compression and decompression.
Fixes: 83cc3b90ad7a ("app/compress-perf: fix testing single operation")
Cc: michae...@nvidia.com
Signed-off-by: Arkadiusz Kusztal
Signed-off-by: Ciara Power
successful run.
Fixes: f8be1786b1b8 ("app/crypto-perf: introduce performance test application")
Cc: sta...@dpdk.org
Signed-off-by: Ciara Power
---
app/test-crypto-perf/cperf_options_parsing.c | 1 +
app/test-crypto-perf/cperf_test_vector_parsing.c | 1 +
2 files changed, 2
The meson driver-tests suite did not include some ipsec_mb SW Crypto
PMD tests, and QAT tests. These are now added to avoid them being missed
if the user runs tests only using the meson suite infrastructure.
Signed-off-by: Ciara Power
---
app/test/meson.build | 5 +
1 file changed, 5
encryption SGL tests for CPU crypto on AESNI_MB
only, as AESNI_GCM CPU crypto supports inplace SGL.
Fixes: f9dfb59edbcc ("crypto/ipsec_mb: support remaining SGL")
Signed-off-by: Ciara Power
---
app/test/test_cryptodev.c | 15 +--
1 file changed, 13 insertions(+), 2 deletion
d-off-by: Ciara Power
---
app/test/test_cryptodev_asym.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/app/test/test_cryptodev_asym.c b/app/test/test_cryptodev_asym.c
index 5b16dcab56..9236817650 100644
--- a/app/test/test_cryptodev_asym.c
+++ b/app
The meson driver-tests suite was missing some QAT and SW PMD
crypto tests, which are now added.
Some issues were highlighted after adding to the driver-tests
suite, which are also addressed in this patchset.
Ciara Power (3):
test/crypto: fix skip condition for CPU crypto SGL
test/crypto
Testcases are added for ZUC256 cipher-auth, auth-cipher,
and auth-cipher-verify.
4 byte, 8 byte, and 16 byte tags are tested for each chained type.
Signed-off-by: Ciara Power
Acked-by: Brian Dooley
---
v2: changed from bit to byte length representation
---
app/test/test_cryptodev.c
("test/crypto: check cipher parameters")
Fixes: f93fce6de4aa ("test/crypto: check auth parameters")
Cc: pablo.de.lara.gua...@intel.com
Cc: sta...@dpdk.org
Signed-off-by: Ciara Power
Acked-by: Brian Dooley
---
app/test/test_cryptodev.c | 27 ---
1 file ch
The incorrect value was being passed to the ZUC authentication test
function, indicating the opposite of the intended GENERATE/VERIFY op.
This is fixed to use the auth op enum rather than a value.
Fixes: 83397b9f0739 ("test/crypto: add further ZUC test cases")
Signed-off-by: Ciara Po
length.
Fixes: 83397b9f0739 ("test/crypto: add further ZUC test cases")
Fixes: fa5bf9345d4e ("test/crypto: add ZUC cases with 256-bit keys")
Cc: vvelum...@marvell.com
Cc: sta...@dpdk.org
Signed-off-by: Ciara Power
Acked-by: Brian Dooley
---
app/test/test_cryptodev.c | 6 ++
length
as this can vary with ZUC256.
Signed-off-by: Ciara Power
Acked-by: Brian Dooley
---
app/test/test_cryptodev.c | 125 +++---
1 file changed, 62 insertions(+), 63 deletions(-)
diff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c
index aa831d79a2
were highlighted when these new tests
were added.
v2: changed bit lengths to byte length representation.
Ciara Power (5):
test/crypto: improve readability of ZUC256 tests
test/crypto: fix ZUC digest length in comparison
test/crypto: fix auth op parameter for ZUC256 tests
test/crypto
Testcases are added for ZUC256 cipher-auth, auth-cipher,
and auth-cipher-verify.
4 byte, 8 byte, and 16 byte tags are tested for each chained type.
Signed-off-by: Ciara Power
---
app/test/test_cryptodev.c | 110
app/test/test_cryptodev_zuc_test_vectors.h | 714
("test/crypto: check cipher parameters")
Fixes: f93fce6de4aa ("test/crypto: check auth parameters")
Cc: pablo.de.lara.gua...@intel.com
Cc: sta...@dpdk.org
Signed-off-by: Ciara Power
---
app/test/test_cryptodev.c | 27 ---
1 file changed, 16 insertions(+), 1
The incorrect value was being passed to the ZUC authentication test
function, indicating the opposite of the intended GENERATE/VERIFY op.
This is fixed to use the auth op enum rather than a value.
Fixes: 83397b9f0739 ("test/crypto: add further ZUC test cases")
Signed-off-by: C
length.
Fixes: 83397b9f0739 ("test/crypto: add further ZUC test cases")
Fixes: fa5bf9345d4e ("test/crypto: add ZUC cases with 256-bit keys")
Cc: vvelum...@marvell.com
Cc: sta...@dpdk.org
Signed-off-by: Ciara Power
---
app/test/test_cryptodev.c | 6 +++---
1 file changed
were highlighted when these new tests
were added.
Ciara Power (5):
test/crypto: improve readability of ZUC256 tests
test/crypto: fix ZUC digest length in comparison
test/crypto: fix auth op parameter for ZUC256 tests
test/crypto: fix capability check for ZUC cipher auth
test/crypto
length
as this can vary with ZUC256.
Signed-off-by: Ciara Power
---
app/test/test_cryptodev.c | 125 +++---
1 file changed, 62 insertions(+), 63 deletions(-)
diff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c
index aa831d79a2..ca7f10557c 100644
--- a
ned-off-by: Ciara Power
---
drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c | 3 +++
drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c | 3 +++
drivers/crypto/qat/qat_sym_session.c | 2 +-
3 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c
("crypto/ipsec_mb: support all tag sizes for ZUC-EIA3-256")
Cc: pablo.de.lara.gua...@intel.com
Signed-off-by: Ciara Power
---
drivers/crypto/ipsec_mb/pmd_aesni_mb.c | 2 +-
drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git
a new variable, this can then be used directly.
The cipher SGL function does not need to buffers allocated for
ciphertext and plaintext, one can be used for both.
Fixes: be8e5d957366 ("test/crypto: add further ZUC testcases")
Signed-off-by: Ciara Power
---
app/test/test_crypto
Previously no ZUC decryption only or hash verify testcases existed,
only encryption and authentication.
This commit adds testcases for ZUC 128 and 256 decryption,
and hash verify.
Signed-off-by: Ciara Power
---
v2: fixed variable initialisation.
---
app/test/test_cryptodev.c | 446
Signed-off-by: Ciara Power
---
drivers/crypto/qat/qat_sym_session.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/crypto/qat/qat_sym_session.c
b/drivers/crypto/qat/qat_sym_session.c
index 0ebc66f89e..c91acc1e9b 100644
--- a/drivers/crypto/qat/qat_sym_session.c
+++
Previously no ZUC decryption only or hash verify testcases existed,
only encryption and authentication.
This commit adds testcases for ZUC 128 and 256 decryption,
and hash verify.
Signed-off-by: Ciara Power
---
app/test/test_cryptodev.c | 444 +++---
1 file
This commit enables asymmetric crypto in generation three
devices.
Signed-off-by: Ciara Power
---
doc/guides/cryptodevs/qat.rst| 3 ++-
doc/guides/rel_notes/release_23_03.rst | 3 +++
drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c | 12
3 files changed, 13
Add support for plain SHA3-224, SHA3-256,
SHA3-384, and SHA3-512 hash support in QAT GEN3.
Add support for SHA3-256 in GEN2.
Signed-off-by: Ciara Power
---
Tested using testcases from patch not yet merged.
https://patchwork.dpdk.org/project/dpdk/patch/20221109152809.2026484-1-vfia
Update the use of outdated language "slaves" with "workers".
Signed-off-by: Ciara Power
---
app/test-crypto-perf/main.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/app/test-crypto-perf/main.c b/app/test-crypto-perf/main.c
index 22f6b2b3ba..af5bd0d
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