Hi,
Since it is only a WA and no need to consider all archs or CPU types, LGTM so
far.
> -Original Message-
> From: Viacheslav Ovsiienko
> Sent: Friday, December 6, 2024 10:26 PM
> To: dev@dpdk.org
> Cc: Raslan Darawsheh ; Matan Azrad ;
> Suanming Mou ; sta...@dpdk.org
> Subject: [PATCH
> > rte_pci_tph_st_{get, set} functions will return an error if processing
> > any of the rte_tph_info objects fails. The API does not indicate which
> > entry in the rte_tph_info array was executed successfully and which
> > caused an error. Therefore, in case of an error, the caller should
> > di
> > Today, DPDK applications benefit from Direct Cache Access (DCA)
> > features like Intel DDIO and Arm's write-allocate-to-SLC. However,
> > those features do not allow fine-grained control of direct cache
> > access, such as stashing packets into upper-level caches (L2 caches)
> > of a processor
Current versions of clang and BPF verifier no longer need
an explicit unroll pragma.
Signed-off-by: Stephen Hemminger
---
drivers/net/tap/bpf/tap_rss.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/net/tap/bpf/tap_rss.c b/drivers/net/tap/bpf/tap_rss.c
index a76f4bfcb3..6a1c3761b7
On Wed, 04 Jun 2025 11:27:18 +0200
Thomas Monjalon wrote:
> 24/04/2025 18:07, Stephen Hemminger:
> > The BPF code in TAP device was using outdated advice on how
> > to write BPF programs. Modern BPF verifier has to do less work
> > if force inlining and unrolling is not done.
>
> Why do you ke
On Thu, 29 May 2025 21:13:42 +0530
wrote:
> From: Kiran Kumar K
>
> On supporting hardware, RoCEv2 header can be used to
> perform RSS in the ingress path.
>
> Signed-off-by: Kiran Kumar K
> ---
> V9 Changes:
> * Fix checkpatch warnings.
> V8 Changes:
> * Fixed doc
> V7 Changes;
> * Addressed
On Fri, 23 May 2025 11:36:05 +0100
Anatoly Burakov wrote:
> When using '?' to find commands, it occasionally is difficult to find the
> needed commands because all commands are not in alphabetical order, but
> rather can be ordered rather arbitrarily.
>
> To address this, use help string to orde
On Mon, 2 Jun 2025 16:10:35 +0530
Gagandeep Singh wrote:
> From: Apeksha Gupta
>
> This patch upgrades the MC firmware release API compatibility
> to 10.39.0. Added mc/fsl_dpmac.h file.
>
> Signed-off-by: Apeksha Gupta
> ---
> drivers/net/dpaa2/mc/fsl_dpmac.h | 490 +
On Thu, Apr 24, 2025 at 7:08 PM Oleksandr Nahnybida
wrote:
>
> Offset should be aligned first before checking if there is free space for
> another write.
>
> Bugzilla ID: 1665
> Fixes: 032a7e5499a0 ("trace: implement provider payload")
Cc: sta...@dpdk.org
>
> Signed-off-by: Oleksandr Nahnybida
>
https://bugs.dpdk.org/show_bug.cgi?id=1678
David Marchand (david.march...@redhat.com) changed:
What|Removed |Added
Resolution|--- |FIXED
St
Hi all,
Please find answers inline
On 03/06/2025 06:54, Nitin Saxena wrote:
Hi Morten,
Let me take a stab regarding the VRF question.
Please find answers inline
Thanks,
Nitin
On Mon, Jun 2, 2025 at 2:12 PM Morten Brørup wrote:
+TO: Robin Jarry, might have relevant feedback for such a node
On Sat, May 17, 2025 at 10:32 AM Yang Ming wrote:
>
> DPDK detect vfio container according the existence of vfio
> module. But for container with non-privileged mode, there is
> possibility that no VFIO_DIR(/dev/vfio) mapping from host to
> container when host have both Intel NIC and Mellanox NIC
Hi Konstantin,
I have some updates to the previous claims I have made.
> > > > That cannot happen in Arm v8/v9 because tail update is a
> > > > store-release and a load-acquire that program order follows it can
> > > > only be issued after all the cores have observed the store-release
> > > > (th
Hi Sunyuechi,
On 04/06/2025 12:39, 孙越池 wrote:
> why is it done in a scalar way instead of using
`__riscv_vsrl_vx_u32m1()?` I assume you're relying on the compiler here?
I don't know the exact reason, but based on experience, using indexed
loads tends to be slower for small-scale and low-comp
On Mon, Jun 02, 2025 at 10:38:02PM +, Wathsala Vithanage wrote:
> Extend the PCI bus driver to enable or disable TPH capability and set or
> get PCI Steering-Tags (STs) on an endpoint device. The functions
> rte_pci_tph_{enable, disable,st_set,st_get} provide the primary
> interface for DPDK de
On Wed, Jun 4, 2025 at 3:43 PM Nitin Saxena wrote:
>
> This patch defines RTE_GRAPH_FEATURE_ARC_REGISTER() and
> RTE_GRAPH_FEATURE_REGISTER() constructors and associated APIs with
> programming guide.
>
> Signed-off-by: Nitin Saxena
> ---
> doc/api/doxy-api-index.md | 1 +
>
Hi Kiran,
On Wed, Jun 4, 2025 at 5:06 PM Kiran Kumar Kokkilagadda
wrote:
>
>
>
> > -Original Message-
> > From: Nitin Saxena
> > Sent: Wednesday, June 4, 2025 3:43 PM
> > To: Jerin Jacob ; Kiran Kumar Kokkilagadda
> > ; Nithin Kumar Dabilpuram
> > ; Zhirun Yan ; Robin
> > Jarry ; Christ
On Thu, Apr 3, 2025 at 4:57 AM Dengdui Huang wrote:
>
> When the process address space is insufficient,
> mmap will fail, which will cause an infinite loop.
> This patch stops attempting mmap if it fails and
> the requested size cannot be reduced.
>
> Fixes: b7cc54187ea4 ("mem: move virtual area f
On Wed, Mar 26, 2025 at 6:14 PM Bruce Richardson
wrote:
>
> The test case "test_multi_alloc_statistics" was brittle in that it did
> some allocations and frees and then checked statistics without
> considering the initial state of the malloc heaps. This meant that,
> depending on what allocations/
Hi Jerin,
On Fri, May 30, 2025 at 6:43 PM Jerin Jacob wrote:
>
>
>
> > -Original Message-
> > From: Nitin Saxena
> > Sent: Monday, April 21, 2025 8:47 PM
> > To: Jerin Jacob ; Kiran Kumar Kokkilagadda
> > ; Nithin Kumar Dabilpuram
> > ; Zhirun Yan ; Robin
> > Jarry ; Christophe Fontaine
Hi Jerin,
I have fixed all your comments in the v10 patchset.
Thanks,
Nitin
On Fri, May 30, 2025 at 6:39 PM Jerin Jacob wrote:
>
>
> > -Original Message-
> > From: Nitin Saxena
> > Sent: Monday, April 21, 2025 8:47 PM
> > To: Jerin Jacob ; Kiran Kumar Kokkilagadda
> > ; Nithin Kumar Da
Hi Kiran,
On Wed, Jun 4, 2025 at 4:54 PM Kiran Kumar Kokkilagadda
wrote:
>
>
>
> > -Original Message-
> > From: Nitin Saxena
> > Sent: Wednesday, June 4, 2025 3:43 PM
> > To: Jerin Jacob ; Kiran Kumar Kokkilagadda
> > ; Nithin Kumar Dabilpuram
> > ; Zhirun Yan ; Robin
> > Jarry ; Christ
From: sunyuechi
This patch is derived from "config/riscv: detect presence of Zbc
extension with modifications".
The RISC-V C api defines architecture extension test macros
These let us detect whether the V extension is supported on the
compiler and -march we're building with. The C api also defi
From: sunyuechi
This patch series adds support for the RISC-V Vector (V) extension and provides
an optimized implementation of `rte_lpm_lookupx4` using RVV. It includes runtime
detection of the V extension, conditional compilation based on compiler support
for RVV intrinsics.
Test results using
From: sunyuechi
Support using -Dcpu_instruction_set=rv64gcv to enable V extension.
Signed-off-by: sunyuechi
---
config/riscv/meson.build | 2 ++
1 file changed, 2 insertions(+)
diff --git a/config/riscv/meson.build b/config/riscv/meson.build
index e3694cf2e6..1036a86d05 100644
--- a/config/ri
From: sunyuechi
Test results using lpm_perf_autotest on BPI-F3:
scalar: 5.7 cycles
rvv:2.4 cycles
The best way to call this RVV function is to follow the approach used in
lib/fib, where all architectures initialize a function pointer in a
unified way. However, other architectures in
On Wed, Jun 4, 2025 at 9:12 PM Nitin Saxena wrote:
>
> New internal API used by feature arc library to override node's original
> process() func.
>
> Signed-off-by: Nitin Saxena
Acked-by: Jerin Jacob
Hi,
On Fri, May 30, 2025 at 05:21:57PM -0700, Andre Muezerie wrote:
> When compiling with MSVC the error below is hit:
>
> drivers\net\mlx5\mlx5_tx.h(1148): error C2065: 'rte_v128u32_t':
> undeclared identifier
>
> Turns out that with MSVC the data type rte_v128u32_t is not used, but
> its s
> On Mon, 26 May 2025 at 14:15, Akhil Goyal wrote:
>
> >
> > DPDK deprecation notice need not include API changes in external libraries.
> > We just need to notify the users about the version of ZSDA external lib is
> > going
> to change in next release or so.
> > And then we can change the cod
- Added ip4 output arc to allow applications to hook feature nodes in ip4
egress direction
- Added interface_tx node as end feature to ip4 output arc
Signed-off-by: Nitin Saxena
---
doc/guides/rel_notes/release_25_07.rst | 2 +
lib/node/ethdev_ctrl.c | 8 +
lib/node/interface
- Added cmdline argument "--enable-graph-feature-arc" to call
rte_graph_feature_arc_init() before rte_graph_create() which creates
in-built arcs and feature nodes
- Added custom feature nodes in app/graph which are added to ip4 output
arc.
- Custom features can be enabled/disabled at runtime
Added functional unit test case for verifying feature arc control plane
and fast path APIs
How to run:
$ echo "graph_feature_arc_autotest" | ./bin/dpdk-test
Signed-off-by: Nitin Saxena
---
app/test/meson.build |1 +
app/test/test_graph_feature_arc.c | 1374 +
This patch also adds feature arc fast path APIs as well along with
documentation
Signed-off-by: Nitin Saxena
---
doc/guides/prog_guide/graph_lib.rst | 180 ++
lib/graph/graph_feature_arc.c| 717 ++-
lib/graph/meson.build| 2 +-
lib/g
This patch defines RTE_GRAPH_FEATURE_ARC_REGISTER() and
RTE_GRAPH_FEATURE_REGISTER() constructors and associated APIs with
programming guide.
Signed-off-by: Nitin Saxena
---
doc/api/doxy-api-index.md | 1 +
doc/guides/prog_guide/graph_lib.rst | 289 +++
doc/gu
This patch adds feature arc init()/create()/destroy() APIs. It also add
APIs for adding feature node to an arc.
Signed-off-by: Nitin Saxena
---
doc/api/doxy-api-index.md|1 +
doc/guides/prog_guide/graph_lib.rst | 27 +-
lib/graph/graph_feature_arc.c| 1327 +
New internal API used by feature arc library to override node's original
process() func.
Signed-off-by: Nitin Saxena
---
lib/graph/graph_private.h | 11 +++
lib/graph/node.c | 22 ++
2 files changed, 33 insertions(+)
diff --git a/lib/graph/graph_private.h b/
Feature arc represents an ordered list of features/protocols at a given
networking layer. It is a high level abstraction to express relationship
between rte_graph nodes, as feature nodes, and allow packets steering
across these nodes in a simplified manner.
Features (or feature nodes) are nodes wh
On Fri, May 30, 2025 at 02:57:21PM +0100, Anatoly Burakov wrote:
> Currently, there are duplicate implementations of Tx mbuf recycle in some
> drivers, specifically ixgbe and i40e. Move them into a common header.
>
> Signed-off-by: Anatoly Burakov
> ---
Acked-by: Bruce Richardson
On Wed, Jun 04, 2025 at 09:42:31AM +0200, Dariusz Sosnowski wrote:
> Hi,
>
> On Tue, Jun 03, 2025 at 06:41:24PM +0200, Dariusz Sosnowski wrote:
> > Hi,
> >
> > On Tue, May 27, 2025 at 04:41:25PM -0700, Andre Muezerie wrote:
> > > When compiling with MSVC, warnings like the one below pop up:
> > >
On Fri, May 30, 2025 at 02:57:20PM +0100, Anatoly Burakov wrote:
> Currently, there are duplicate implementations of Rx mbuf recycle in some
> drivers, specifically ixgbe and i40e. Move them into a common header.
>
> While we're at it, also support no-IOVA-in-mbuf case.
>
> Signed-off-by: Anatoly
Hi,
On 28/05/2025 2:41 AM, Andre Muezerie wrote:
When compiling with MSVC, warnings like the one below pop up:
../drivers/common/mlx5/mlx5_devx_cmds.c(554): warning C5287: operands
are different enum types
'' and
''; use an explicit cast
to silence this warning
The values
Hi,
On 05/05/2025 6:04 PM, Andre Muezerie wrote:
Builtin __builtin_ffsl is not available with MSVC therefore a
portable replacement should be used.
Function rte_ffs32 is already available in eal and should be used
instead.
Signed-off-by: Andre Muezerie
Patch applied to next-net-mlx,
Kinde
Hi,
On 05/05/2025 6:16 PM, Andre Muezerie wrote:
When compiling with MSVC, errors like the one below pop up:
../drivers/crypto/mlx5/mlx5_crypto_xts.c(488): warning C4334:
'<<': result of 32-bit shift implicitly converted to 64 bits
(was 64-bit shift intended?)
Depending on the situat
Hi,
On 05/05/2025 5:45 PM, Andre Muezerie wrote:
When compiling DPDK with mlx5 using clang on Windows with
"debug" buildtype the error below is hit:
net_mlx5_mlx5_flow_dv.c.obj : error LNK2019: unresolved external symbol
mlx5_geneve_tlv_parser_create referenced in function
flow_dv_di
Hi,
On 25/04/2025 6:55 PM, Alexander Kozyrev wrote:
Enqueue generated counter IDs on a ring in bulk.
Generate them and store in an array before putting them
on a ring all at once. That bring better cache access
and speeds up the mlx5_hws_cnt_pool_create() function.
Signed-off-by: Alexander Koz
On Fri, May 30, 2025 at 02:57:19PM +0100, Anatoly Burakov wrote:
> Currently, for 32-byte descriptor format, only SSE instruction set is
> supported. Add implementation for AVX2 and AVX512 instruction sets. Since
> we are using Rx descriptor definitions from common code, we can just use
> the gener
On Wed, Jun 04, 2025 at 03:13:55PM +0100, Bruce Richardson wrote:
> On Wed, Apr 16, 2025 at 02:44:55PM -0700, Andre Muezerie wrote:
> > DPDK uses GCC attribute "used" through macro __rte_used to indicate
> > that a variable not referenced in the code should be assumed being
> > used and therefore n
When compiling with MSVC the errors below are hit because msvc does not
support inline assembly:
1)
../drivers/common/mlx5/mlx5_common.c(86): warning C4013: '__asm__'
undefined; assuming extern returning int
../drivers/common/mlx5/mlx5_common.c(87): error C2143: syntax error:
missing ')'
On Tue, Jun 03, 2025 at 05:13:14PM +0200, Dariusz Sosnowski wrote:
> Hi,
>
> On Mon, May 05, 2025 at 07:57:42AM -0700, Andre Muezerie wrote:
> > When compiling with MSVC the errors below are hit because msvc does not
> > support inline assembly:
> >
> > 1)
> > ../drivers/common/mlx5/mlx5_common.c
On Wed, Apr 16, 2025 at 02:44:55PM -0700, Andre Muezerie wrote:
> DPDK uses GCC attribute "used" through macro __rte_used to indicate
> that a variable not referenced in the code should be assumed being
> used and therefore not be optimized away. This technique is used to embed
> information in the
On Wed, Jun 04, 2025 at 01:04:29PM +0200, David Marchand wrote:
> Hello Andre,
>
> On Wed, Apr 16, 2025 at 11:45 PM Andre Muezerie
> wrote:
> >
> > The archiver tool from the MSVC toolset is lib.exe. It has different
> > parameters then it's GNU counterpart "ar".
> >
> > buildtools\meson.build wa
On Wed, Jun 04, 2025 at 02:03:56PM +0200, David Marchand wrote:
> On Tue, Jun 3, 2025 at 3:01 AM Andre Muezerie
> wrote:
> >
> > On Wed, Apr 16, 2025 at 02:44:54PM -0700, Andre Muezerie wrote:
> > > DPDK uses GCC attribute "used" through macro __rte_used to indicate
> > > that a variable not refer
DPDK uses GCC attribute "used" through macro __rte_used to indicate
that a variable not referenced in the code should be assumed being
used and therefore not be optimized away. This technique is used to embed
information in the binaries, by having crafted information stored in
them.
MSVC offers si
The archiver tool from the MSVC toolset is lib.exe. It has different
parameters then it's GNU counterpart "ar".
buildtools\meson.build was updated to use lib.exe when MSVC compiler is
used. This is to allow the code to be built without requiring GNU "ar"
to be installed in that scenario.
Script g
Script usertools\dpdk-pmdinfo.py was enhanced to also be able to parse
symbols from sections in PE images.
Signed-off-by: Andre Muezerie
---
usertools/dpdk-pmdinfo.py | 53 +++
1 file changed, 43 insertions(+), 10 deletions(-)
diff --git a/usertools/dpdk-pmdi
DPDK uses GCC attribute "used" through macro __rte_used to indicate
that a variable not referenced in the code should be assumed being
used and therefore not be optimized away. This technique is used to embed
information in the binaries, by having crafted information stored in
them.
MSVC offers si
DPDK uses GCC attribute "used" through macro __rte_used to indicate
that a variable not referenced in the code should be assumed being
used and therefore not be optimized away. This technique is used to embed
information in the binaries, by having crafted information stored in
them.
MSVC offers si
The previous v2 patch incorrectly used --in-reply-to, which caused a warning on
Patchwork. This update only corrects the Reply-To field.
> -原始邮件-
> 发件人: u...@foxmail.com
> 发送时间: 2025-06-04 21:07:33 (星期三)
> 收件人: dev@dpdk.org
> 抄送: sunyuechi
> 主题: [PATCH v2 0/3] Add RISC-V V extension det
From: sunyuechi
Support using -Dcpu_instruction_set=rv64gcv to enable V extension.
Signed-off-by: sunyuechi
---
config/riscv/meson.build | 2 ++
1 file changed, 2 insertions(+)
diff --git a/config/riscv/meson.build b/config/riscv/meson.build
index e3694cf2e6..1036a86d05 100644
--- a/config/ri
From: sunyuechi
Test results using lpm_perf_autotest on BPI-F3:
scalar: 5.7 cycles
rvv:2.4 cycles
The best way to call this RVV function is to follow the approach used in
lib/fib, where all architectures initialize a function pointer in a
unified way. However, other architectures in
From: sunyuechi
This patch series adds support for the RISC-V Vector (V) extension and provides
an optimized implementation of `rte_lpm_lookupx4` using RVV. It includes runtime
detection of the V extension, conditional compilation based on compiler support
for RVV intrinsics.
Test results using
From: sunyuechi
This patch is derived from "config/riscv: detect presence of Zbc
extension with modifications".
The RISC-V C api defines architecture extension test macros
These let us detect whether the V extension is supported on the
compiler and -march we're building with. The C api also defi
From: Pavan Nikhilesh
Add event vector adapter support to CN20K event device.
Signed-off-by: Pavan Nikhilesh
---
v2 Changes:
- Add depends on series tag.
- Fix compilation.
v3 Changes:
- Rebase.
- Fix errors from check-meson.py
drivers/common/cnxk/roc_sso.c | 4 +-
drivers/comm
On Fri, May 30, 2025 at 02:57:19PM +0100, Anatoly Burakov wrote:
> Currently, for 32-byte descriptor format, only SSE instruction set is
> supported. Add implementation for AVX2 and AVX512 instruction sets. Since
> we are using Rx descriptor definitions from common code, we can just use
> the gener
On Mon, Dec 23, 2024 at 10:11 PM Andre Muezerie
wrote:
>
> Test fib6_perf_autotest was hitting a stack overflow on Windows
> with MSVC.
>
> The fix is to move some of the data from the stack to the heap.
>
> Signed-off-by: Andre Muezerie
> Acked-by: Vladimir Medvedkin
Applied, thanks.
--
Dav
On Mon, 26 May 2025 at 14:15, Akhil Goyal wrote:
>
> DPDK deprecation notice need not include API changes in external libraries.
> We just need to notify the users about the version of ZSDA external lib is
> going to change in next release or so.
> And then we can change the code.
>
> You can re
On Tue, Jun 3, 2025 at 3:01 AM Andre Muezerie
wrote:
>
> On Wed, Apr 16, 2025 at 02:44:54PM -0700, Andre Muezerie wrote:
> > DPDK uses GCC attribute "used" through macro __rte_used to indicate
> > that a variable not referenced in the code should be assumed being
> > used and therefore not be opti
From: sunyuechi
Test results using lpm_perf_autotest on BPI-F3:
scalar: 5.7 cycles
rvv:2.4 cycles
The best way to call this RVV function is to follow the approach used in
lib/fib, where all architectures initialize a function pointer in a
unified way. However, other architectures in
From: sunyuechi
Support using -Dcpu_instruction_set=rv64gcv to enable V extension.
Signed-off-by: sunyuechi
---
config/riscv/meson.build | 2 ++
1 file changed, 2 insertions(+)
diff --git a/config/riscv/meson.build b/config/riscv/meson.build
index e3694cf2e6..1036a86d05 100644
--- a/config/ri
From: sunyuechi
Test results using lpm_perf_autotest on BPI-F3:
scalar: 5.7 cycles
rvv:2.4 cycles
The best way to call this RVV function is to follow the approach used in
lib/fib, where all architectures initialize a function pointer in a
unified way. However, other architectures in
From: sunyuechi
This patch is derived from "config/riscv: detect presence of Zbc
extension with modifications".
The RISC-V C api defines architecture extension test macros
These let us detect whether the V extension is supported on the
compiler and -march we're building with. The C api also defi
From: sunyuechi
This patch series adds support for the RISC-V Vector (V) extension and provides
an optimized implementation of `rte_lpm_lookupx4` using RVV. It includes runtime
detection of the V extension, conditional compilation based on compiler support
for RVV intrinsics.
Test results using
> why is it done in a scalar way instead of using `__riscv_vsrl_vx_u32m1()?` I
> assume you're relying on the compiler here?
I don't know the exact reason, but based on experience, using indexed loads
tends to be slower for small-scale and low-computation cases. So I've tried
both methods.
In t
04/06/2025 13:04, Morten Brørup:
> > From: David Marchand [mailto:david.march...@redhat.com]
> > Sent: Wednesday, 4 June 2025 12.41
> >
> > On Wed, Jun 4, 2025 at 12:29 PM Morten Brørup
> > wrote:
> > > > I am not a fan of adding such public API, an internal API would be
> > > > enough.
> > > > D
> -Original Message-
> From: Nitin Saxena
> Sent: Wednesday, June 4, 2025 3:43 PM
> To: Jerin Jacob ; Kiran Kumar Kokkilagadda
> ; Nithin Kumar Dabilpuram
> ; Zhirun Yan ; Robin
> Jarry ; Christophe Fontaine
> Cc: dev@dpdk.org; Nitin Saxena
> Subject: [PATCH v10 4/7] graph: add featur
From: sunyuechi
Support using -Dcpu_instruction_set=rv64gcv to enable V extension.
Signed-off-by: sunyuechi
---
config/riscv/meson.build | 2 ++
1 file changed, 2 insertions(+)
diff --git a/config/riscv/meson.build b/config/riscv/meson.build
index e3694cf2e6..1036a86d05 100644
--- a/config/ri
From: sunyuechi
This patch is derived from "config/riscv: detect presence of Zbc
extension with modifications".
The RISC-V C api defines architecture extension test macros
These let us detect whether the V extension is supported on the
compiler and -march we're building with. The C api also defi
From: sunyuechi
This patch series adds support for the RISC-V Vector (V) extension and provides
an optimized implementation of `rte_lpm_lookupx4` using RVV. It includes runtime
detection of the V extension, conditional compilation based on compiler support
for RVV intrinsics.
Test results using
> -Original Message-
> From: Nitin Saxena
> Sent: Wednesday, June 4, 2025 3:43 PM
> To: Jerin Jacob ; Kiran Kumar Kokkilagadda
> ; Nithin Kumar Dabilpuram
> ; Zhirun Yan ; Robin
> Jarry ; Christophe Fontaine
> Cc: dev@dpdk.org; Nitin Saxena
> Subject: [PATCH v10 3/7] graph: add featur
> From: David Marchand [mailto:david.march...@redhat.com]
> Sent: Wednesday, 4 June 2025 12.41
>
> On Wed, Jun 4, 2025 at 12:29 PM Morten Brørup
> wrote:
> > > I am not a fan of adding such public API, an internal API would be
> > > enough.
> > > Do you plan to add more helpers for math operation
On Tue, Jun 3, 2025 at 7:54 PM Dariusz Sosnowski wrote:
> > Atm, I don't see the need for keeping such a cached mtu value in priv.
> > There is only one user of the value, and it is for configuration
> > operation that can do a query to the kernel.
>
> I agree. It's not really needed, especially s
Hello Andre,
On Wed, Apr 16, 2025 at 11:45 PM Andre Muezerie
wrote:
>
> The archiver tool from the MSVC toolset is lib.exe. It has different
> parameters then it's GNU counterpart "ar".
>
> buildtools\meson.build was updated to use lib.exe when MSVC compiler is
> used. This is to allow the code t
> From: Bruce Richardson [mailto:bruce.richard...@intel.com]
> Sent: Wednesday, 4 June 2025 11.49
>
> On Wed, Jun 04, 2025 at 11:43:01AM +0200, Morten Brørup wrote:
> > > From: Bruce Richardson [mailto:bruce.richard...@intel.com]
> > > Sent: Wednesday, 4 June 2025 11.32
> > >
> > > On Fri, May 30,
24/04/2025 18:07, Stephen Hemminger:
> The BPF code in TAP device was using outdated advice on how
> to write BPF programs. Modern BPF verifier has to do less work
> if force inlining and unrolling is not done.
Why do you keep unroll in IPv6 parsing?
> -Original Message-
> From: Nitin Saxena
> Sent: Wednesday, June 4, 2025 3:42 PM
> To: Jerin Jacob ; Kiran Kumar Kokkilagadda
> ; Nithin Kumar Dabilpuram
> ; Zhirun Yan ; Robin
> Jarry ; Christophe Fontaine
> Cc: dev@dpdk.org; Nitin Saxena
> Subject: [PATCH v10 1/7] graph: add API to
On Wed, Jun 4, 2025 at 12:29 PM Morten Brørup
wrote:
> > I am not a fan of adding such public API, an internal API would be
> > enough.
> > Do you plan to add more helpers for math operations?
> >
> > For the current helper, the only user is a driver (base code).
> > Can't we just wrap a __builti
On Wed, May 7, 2025 at 4:21 PM Andre Muezerie
wrote:
>
> When compiling drivers on Windows, instances have been seen where a
> temporary directory fails to get cleaned up due to
> ERROR_SHARING_VIOLATION (32).
>
> This issue was not seen on operating systems other than Windows.
>
> This patch elim
> From: David Marchand [mailto:david.march...@redhat.com]
> Sent: Wednesday, 4 June 2025 12.08
>
> On Fri, Mar 14, 2025 at 3:34 PM Andre Muezerie
> wrote:
> >
> > __builtin_add_overflow is gcc specific. There's a need for a portable
> > version that can also be used with other compilers.
> >
> >
This patch adds feature arc init()/create()/destroy() APIs. It also add
APIs for adding feature node to an arc.
Signed-off-by: Nitin Saxena
---
doc/api/doxy-api-index.md|1 +
doc/guides/prog_guide/graph_lib.rst | 23 +-
lib/graph/graph_feature_arc.c| 1329 +
Added functional unit test case for verifying feature arc control plane
and fast path APIs
How to run:
$ echo "graph_feature_arc_autotest" | ./bin/dpdk-test
Signed-off-by: Nitin Saxena
---
app/test/meson.build |1 +
app/test/test_graph_feature_arc.c | 1374 +
- Added cmdline argument "--enable-graph-feature-arc" to call
rte_graph_feature_arc_init() before rte_graph_create() which creates
in-built arcs and feature nodes
- Added custom feature nodes in app/graph which are added to ip4 output
arc.
- Custom features can be enabled/disabled at runtime
This patch also adds feature arc fast path APIs as well along with
documentation
Signed-off-by: Nitin Saxena
---
doc/guides/prog_guide/graph_lib.rst | 180 ++
lib/graph/graph_feature_arc.c| 701 ++-
lib/graph/meson.build| 2 +-
lib/g
- Added ip4 output arc to allow applications to hook feature nodes in ip4
egress direction
- Added interface_tx node as end feature to ip4 output arc
Signed-off-by: Nitin Saxena
---
doc/guides/rel_notes/release_25_07.rst | 2 +
lib/node/ethdev_ctrl.c | 8 +
lib/node/interface
This patch defines RTE_GRAPH_FEATURE_ARC_REGISTER() and
RTE_GRAPH_FEATURE_REGISTER() constructors and associated APIs with
programming guide.
Signed-off-by: Nitin Saxena
---
doc/api/doxy-api-index.md | 1 +
doc/guides/prog_guide/graph_lib.rst | 289 +++
doc/gu
New internal API used by feature arc library to override node's original
process() func.
Signed-off-by: Nitin Saxena
---
lib/graph/graph_private.h | 11 +++
lib/graph/node.c | 23 +++
2 files changed, 34 insertions(+)
diff --git a/lib/graph/graph_private.h b
Feature arc represents an ordered list of features/protocols at a given
networking layer. It is a high level abstraction to express relationship
between rte_graph nodes, as feature nodes, and allow packets steering
across these nodes in a simplified manner.
Features (or feature nodes) are nodes wh
On Fri, Mar 14, 2025 at 3:34 PM Andre Muezerie
wrote:
>
> __builtin_add_overflow is gcc specific. There's a need for a portable
> version that can also be used with other compilers.
>
> v5:
> - Combined patches 1 with 5 and 2 with 3.
>
> v4:
> - Added define in ice_osdep.h to use portable version
Hello, Maxime
Thank you for your review.
If I understand correctly, you propose modifying the VHOST_USER_ASSERT_LOCK()
macro so that a VHOST_USER_SET_MEM_TABLE request does not trigger an assertion.
However, I believe such modification would not be appropriate, as it would
revert the logic intro
On Fri, May 30, 2025 at 02:57:15PM +0100, Anatoly Burakov wrote:
> There is certain amount of duplication between various drivers when it
> comes to Rx ring rearm. This patch takes implementation from ice driver
> as a base because it has support for no IOVA in mbuf as well as all
> vector implemen
On Wed, Jun 04, 2025 at 11:43:01AM +0200, Morten Brørup wrote:
> > From: Bruce Richardson [mailto:bruce.richard...@intel.com]
> > Sent: Wednesday, 4 June 2025 11.32
> >
> > On Fri, May 30, 2025 at 02:57:15PM +0100, Anatoly Burakov wrote:
> > > There is certain amount of duplication between various
1 - 100 of 112 matches
Mail list logo
