RE: [C++] Runtime SIMD dispatching for Arrow

, 2020 at 10:29 PM Du, Frank wrote: > > Just want to give some updates on the dispatching. > > Now we has workable runtime functionality include dispatch mechanism[1][2] > and build framework for both the compute kernels and other parts of C++. > There are some remaining SIMD st

RE: [C++] Runtime SIMD dispatching for Arrow

Just want to give some updates on the dispatching. Now we has workable runtime functionality include dispatch mechanism[1][2] and build framework for both the compute kernels and other parts of C++. There are some remaining SIMD static complier code under the code base that I will try to work l

RE: [C++][Discuss] Approaches for SIMD optimizations

e hooks based on CPU manufacturer, which for BMI2 intrinsics would be a requirement. The alternative would be to ban BMI2 intrinsics from the code (this might not be a bad idea to limit complexity in general). Thoughts? Thanks, Micah On Wed, Jun 10, 2020 at 8:35 PM Du, Frank wrote: > Thanks

RE: [C++][Discuss] Approaches for SIMD optimizations

me secret for me. Thanks, Frank -Original Message- From: Jed Brown Sent: Thursday, June 11, 2020 1:58 AM To: Du, Frank ; dev@arrow.apache.org Subject: RE: [C++][Discuss] Approaches for SIMD optimizations "Du, Frank" writes: > The PR I committed provide a basic support for

RE: [C++][Discuss] Approaches for SIMD optimizations

The PR I committed provide a basic support for runtime dispatching. I agree that complier should generate good vectorize for the non-null data part but in fact it didn't, jedbrown point to it can force complier to SIMD using some additional pragmas, something like "#pragma omp simd reduction(+:

RE: [C++] Runtime SIMD dispatching for Arrow

Hi, I totally agree that arrow should has a built-in support for runtime dispatching facilities just like other popular computing libs to fully utilize the modern hardware capacity, we feel arrow has great potential performance chance with the advanced cpu SIMD feature. It's ok for me to stop

Vendor direction for SSE operations on Spaced Decode/Encode

Hi All, Currently we are working on SIMD chance to improves speed of DecodeSpaced on Jira, the path for AVX512 is identified with the helper of vpcompressd/vpexpandd instructions. I has uploaded the PR