* Sergei Poselenov | 2010-09-21 14:54:22 [+0400]:
>Hello Sebastian,
Hi Sergei,
>Should the bug 44606 trigger on a e500v1 CPU?
>
>I can check it with gcc 4.2.2 on a MPC8560 system.
SPE support got merged in gcc 4.3. An e500v1 CPU does not have support
for the type "double" so you shouldn't be able
* Sergei Poselenov | 2010-09-21 14:09:24 [+0400]:
>Hello Sebastian,
Hi Sergei,
>BTW, do you know - why the separate target for e500? Is the instruction
>set for e500 so fundamentally different it needs a special configuration
>for GCC? Why GCC cannot switch codegeneration at run-time, conditionin
I promised some details about my hardware.
So I can participate to testing with a Power5 pSeries CHRP IBM 9113-550, an
U320 raid controller (ibm5709) in it.
Actually, I'm playing with the installation of the weekly build.
I also have some older hardware but i dont think anyone is interested in
Hello Sebastian,
Should the bug 44606 trigger on a e500v1 CPU?
I can check it with gcc 4.2.2 on a MPC8560 system.
Regards,
Sergei
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Hello Sebastian,
On Sun, 19 Sep 2010 22:35:27 +0200
Sebastian Andrzej Siewior wrote:
> * Sergei Poselenov | 2010-09-18 11:44:01 [+0400]:
>
>
> >Thanks, but I'm looking for specific information - what instruction
> >set was used by gcc to build Debian binaries.
> >
> >It seems to me this infor
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