cvs commit: src/sys/sparc64/include asi.h tlb.h src/sys/sparc64/sparc64 cheetah.c genassym.c pmap.c swtch.S

2008-09-08 Thread Marius Strobl
marius 2008-09-08 21:24:25 UTC FreeBSD src repository Modified files: sys/sparc64/include asi.h tlb.h sys/sparc64/sparc64 cheetah.c genassym.c pmap.c swtch.S Log: SVN rev 182878 on 2008-09-08 21:24:25Z by marius For cheetah-class CPUs ensure that the dt512_0 is set t

cvs commit: src/sys/sparc64/include asi.h cache.h cpufunc.h pcpu.h src/sys/sparc64/sparc64 cheetah.c clock.c exception.S locore.S machdep.c mp_locore.S mp_machdep.c pmap.c prof_machdep.c spitfire.c su

2008-08-13 Thread Marius Strobl
marius 2008-08-13 20:30:28 UTC FreeBSD src repository Modified files: sys/sparc64/include asi.h cache.h cpufunc.h pcpu.h sys/sparc64/sparc64 cheetah.c clock.c exception.S locore.S machdep.c mp_locore.S mp_machdep.c pmap.c pro

cvs commit: src/sys/sparc64/include asi.h

2006-03-31 Thread Marius Strobl
marius 2006-03-31 23:40:42 UTC FreeBSD src repository Modified files:(Branch: RELENG_6) sys/sparc64/include asi.h Log: MFC: 1.10 Add convenience macros for the bits in ASI_ESTATE_ERROR_EN_REG (used for ECC handling) and the additional uses of the ASIs 0x77 and 0x

cvs commit: src/sys/sparc64/include asi.h

2006-03-28 Thread Marius Strobl
marius 2006-03-29 00:08:48 UTC FreeBSD src repository Modified files: sys/sparc64/include asi.h Log: Add convenience macros for the bits in ASI_ESTATE_ERROR_EN_REG (used for ECC handling) and the additional uses of the ASIs 0x77 and 0x7f as well as their bits (used for a CP