cvs commit: src/sys/dev/ciss ciss.c cissreg.h

2008-08-28 Thread Scott Long
scottl 2008-08-29 01:23:16 UTC FreeBSD src repository Modified files: sys/dev/ciss ciss.c cissreg.h Log: SVN rev 182422 on 2008-08-29 01:23:16Z by scottl Work again to fix the interrupt masking problems. We now recognize that there are 3 different interrupt enabl

cvs commit: src/sys/dev/ciss ciss.c cissreg.h

2008-08-02 Thread Scott Long
scottl 2008-08-02 13:04:26 UTC FreeBSD src repository Modified files: sys/dev/ciss ciss.c cissreg.h Log: SVN rev 181177 on 2008-08-02 13:04:26Z by scottl Correctly set the interrupt enable and disable bits. The previous code interfered with Performant mode and le

cvs commit: src/sys/dev/ciss ciss.c cissreg.h

2005-12-30 Thread Paul Saab
ps 2005-12-31 06:28:58 UTC FreeBSD src repository Modified files:(Branch: RELENG_4) sys/dev/ciss ciss.c cissreg.h Log: MFC: revision 1.67 It seems ciss should ignore overrun and underrun on a SCSI INQUIRY command. This fixes some weird booting issues o