On Fri, December 15, 2017 10:00 am, Ivan Ivanov wrote:
> awokd, could you please answer some questions:
>
> 1) From where you got that 0x06001119 microcode patch?
> Is it a trusted source of a microcode? (hope its directly from AMD)
>
>
> 2) Is there any way to determine that 0x06001119 is really t
On Fri, December 15, 2017 11:10 am, Daniel K wrote:
> Starting up with coreboot and SeaBIOS, the screen is completely black for
> around 30 seconds before my on-disc bootloader (grub2) is loaded and
> displayed.
>
> I'm assuming SeaBIOS counts down with some timer before launching the
> on-disc bo
On Sun, December 17, 2017 7:54 pm, Daniel K wrote:
>
> Gave CONFIG_ONBOARD_VGA_IS_PRIMARY=y a try but I ran into the issue you
> warned about where it bricks my system: after the boot sequence, the OS
> only sees the onboard vga and never uses the PCIe video card. Made sure
> by connecting two work
On Mon, December 18, 2017 5:01 am, Matt DeVillier wrote:
> On Sun, Dec 17, 2017 at 6:58 PM, taii...@gmx.com wrote:
>
>
>> On 12/17/2017 05:06 PM, Dame Más wrote:
>>
>>
>> Hi,
>>
>>> The Coreboot BIOS of Purism 13 is open?
>>>
>>>
>> No it isn't, while they do use coreboot the silicon init process
On Thu, January 11, 2018 10:05 am, Nico Huber wrote:
> On 11.01.2018 03:55, taii...@gmx.com wrote:
>> only one coreboot compatible laptop with open source hardware initiation
>> that is remotely secure (lenovo g505s as has a pre-PSP AMD CPU) and
>> theoretically owner controllable
>
> you seem to
Could someone familiar with the AGESA codebase please take over or rework
and resubmit what I attempted to do in https://review.coreboot.org/22843?
There are two problems with my version:
A) Microcode blob should go in 3rdparty/blobs and CBFS- completely agree
and understand the reasoning. I found
[Sorry for the double post; messed up threading on my first attempt. Also
added offer to help test.]
Could someone familiar with the AGESA codebase please take over or rework
and resubmit what I attempted to do in https://review.coreboot.org/22843?
There are two problems with my version:
A) Micro
On Thu, January 18, 2018 6:37 pm, Nico Huber wrote:
> Generally, you can expect microservers with coreboot nowadays (anything
> supported by Intel's IoT group).
If you're talking IoT range, AMD APU Coreboot can be seen at
http://www.pcengines.ch/apu2.htm for example.
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On Tue, March 6, 2018 1:58 am, Gregg Levine wrote:
> Hello!
> That's a great reason right there. Who knows how much they contributed
> to the state of the art, and did not properly sign it. But in the end while
> their world was collapsing around them, we knew who they were via Groklaw.
> -
>
On Tue, March 6, 2018 9:22 am, Carl-Daniel Hailfinger wrote:
>
> Besides that, any project knowingly accepting code from an entity known
> for questionable provenance of submitted code would itself become an easy
> target for lawsuits.
Sorry, bad idea then- will retract.
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On Sun, March 25, 2018 3:21 pm, thierry.laur...@gmail.com wrote:
> On 03/23/2018 05:22 PM, taii...@gmx.com wrote:
>
>> Please also keep in mind that it is impossible to disable ME.
>>
> That is not a binary yes/no fact.
>
>
> Depending of the ME version, it is possible to deactivate it.
> The follo
On Tue, April 17, 2018 7:30 am, Rudolf Marek wrote:
> Hi,
>
>
> I found new microcode here [1], I used
> cpu00610F01_ver0600111F_2018-03-05_AC55EB96.bin as a microcode for my
> Trinity family15h CPU.
> I hacked together a new microcode header which contains the equivalence
> table etc to be able to
On Tue, April 17, 2018 10:31 am, Rudolf Marek wrote:
> Hi,
>
>
> Dne 17.4.2018 v 12:09 awokd via coreboot napsal(a):
>
>> At what byte locations in the header is the equivalence table? I was
>> looking for this...
>
> Hm I'm not aware where is it d
On Tue, April 24, 2018 11:31 pm, Nico Huber wrote:
> On 25.04.2018 00:18, taii...@gmx.com wrote:
>> I can't believe everyone else is so nonchalant about all this
>> considering how important it is I still haven't figured out how to update
>> the microcode on any of my computers - no guides I have
On Thu, April 26, 2018 5:09 pm, Pierre P wrote:
> Hi,
>
>
> I have a KCMA-D8 and am willing to provide a status update but have no
> idea what is the formal way to do it.
>
> I guess it begins with testing a specific version (4.7 or latest source
> ?). Please could you point me to a procedure.
Loo
On Thu, April 26, 2018 11:13 pm, Duncan wrote:
> How urgent is "urgent" given that the board remains in git, and all it
> takes is for a new board status to be submitted (and any bugs fixed)?
>
> If it is so urgent, why don't you submit a report instead of phrasing
> your email in a panic-like and
On Wed, August 8, 2018 3:03 pm, Mike Banon wrote:
> It seems that now the microcode loading for AMD fam15h CPUs, including
> for A10-5750M fam15h Richland CPU found at coreboot-supported Lenovo G505S,
> is supposed to be done in two steps:
>
> 1) First of all it is initializing with this microcode
On Fri, August 17, 2018 11:00 pm, Mike Banon wrote:
> After some research I've discovered serious problems with
> "update_microcode" method:
That's unfortunate, but understandable. The AGESA code is convoluted.
Would it be possible for someone (myself included) to copy
update_microcode.c into the
On Wed, August 29, 2018 9:41 pm, Youness Alaoui wrote:
>
> We're about to get full control back of the ME. I've been working for
> the past few weeks on reproducing the PTResearch buffer overflow exploit on
> the ME, and yesterday they released a PoC for Apollolake (in case you
> missed it : https
Anac:
Greetings
Following various recommendations on Lenovo G505s, I finally got myself
a A10-5750M with dedicated GPU. At least I think it has dedicated
graphics, due to the following output:
# inxi -G
Card-1: AMD Richland [Radeon HD 8650G]
Card-2: AMD Sun Pro [Radeon HD 8570A/8570M]
Whil
Mike Banon:
Problem here is that the latest AMD microcodes officially released by
AMD at linux-firmware.git are far from being the latest... AMD's f15h
recent May 2018 commit contains a version 0x6001119 [2012-07-13]
microcode for TN (CPU ID 0x610F01). Although thats slightly more
recent than
Tom Psyborg:
Hi
Is there any basic code in coreboot tree for recent AMD APUs ?
Specifically Bristol Ridge FX-9830P is of my interest, how much work
is needed to get laptop booting it?
What is the family code for that CPU? If it's f16kb, there is support.
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bernd...@web.de:
Hi. I've watched a television broadcast where a hacker or security expert
suspected that the BIOS of ThinkPads has a backdoor. Therefore, he said he uses
OpenBIOS or coreboot.
I read on Wikipedia that OpenBIOS works in interaction with coreboot on Intel
machines.
I read http
bernd...@web.de:
What do you recommend to use instead if I'd like to replace my current BIOS?
Should I install coreinfo and carry on with
https://doc.coreboot.org/tutorial/part1.html? Should I use SeaBIOS and is there
a tutorial for SeaBIOS, too?
Continuing with the tutorial link and choosing
Patrick Georgi via coreboot:
On 25.11.21 17:04, Mike Banon wrote:
2. It's not just the loss of boards - it's also the loss of coreboot
users/contributors who only have these boards and don't want to switch
These users didn't contribute fixes to their boards (or even just
feedback that things n
Arthur Heymans:
https://review.coreboot.org/c/coreboot/+/48210 and
https://review.coreboot.org/c/coreboot/+/48262/ provided the implementation
for PARALLEL_MP on qemu.
Notice that modern AMD CPUs (soc/amd/¨*) also use PARALLEL_MP and can be
used as an example for AMD AGESA platforms too.
Good l
Nico Huber:
I'll list some thoughts what could be done. Feel free to agree to or
dismiss any of it. Some things are mutually exclusive, others are not.
Thank you for the well written summary. Have been asking myself some of
the same questions. Lack the experience to make a recommendation for
Nico Huber:
On 29.11.21 14:49, awokd wrote:
Branching
-
I know some people are easily offended by the thought, but I want to
mention it anyway as it seems to me like a cheap solution for the com-
munity as a whole. We could maintain platforms on separate branches.
Is this different th
Hans Jürgen Kitter:
Hi All,
I thought that I share with the G505S+Coreboot (+QubesOS) users that I
finally managed to enable and use the dGPUs on the G505S boards.
Nice hacking! I know Mike Banon was working with some others on this
too, hopefully you were able to compare notes. Any benefits
Frederic Dumas wrote on 2/13/19 4:55 PM:
Hi !
Thanks to a face to face talk at FOSDEM 2019 in Brussels, with Philippe,
a German Coreboot speaker (and developer ? He knows better than me), I
was said that dropping a mail to the list and asking for possible
support of my desktop motherboard wo
Coins wrote on 4/3/19 3:50 PM:
Dear Stefan, Alex,
Thank you for your response and information provided.
Indeed open source BIOS would not be less secure than proprietary BIOS,
even quite the opposite is what I would expect.
Basically what I am wondering is, are there any security benefits fro
Chris Laprise:
I might put firmware code analysis on my bucket list for the next life,
if I convert to Buddhism. :)
FWIW, those AMD CPU microcode updates are encrypted, so you should also
include cryptanalysis on your bucket list. Don't believe the video ones
are, though.
__
Mike Banon:
It's strange that you got a variable degree of this USB issue at
different laptops, it should've been the same regardless of your dGPU
type. Seems to be a Qubes-only problem, a bit random, and might be
possible to fix if you'd read a note here -
http://dangerousprototypes.com/docs/Le
Mike Banon:
Huge Thanks to Martin Roth, finally we got a permission from AMD to
merge the new microcode patches - and Martin has just merged them !
;-) So the things became slightly easier and luckily now you could
disregard some microcode-related parts of my last message. And we need
to walk the
miel...@t-online.de:
Toshiba Tecra S4
Model No. PTS40E-01K00JGR
SERIAL No. 27056280H
Dear ladies and gentlemen,
I could compile coreboot. A test with qemu, as described in coreboot -
lesson 1
was successful. But this configuration with mainboard = emulation is for
demon-
stration only, isn't
Michal Zygowski:
On 01.07.2019 14:53, Andriy Gapon wrote:
It appears that HPET MSI support
is disabled on some platforms by default:
src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/Family/Hudson2/EnvDefHudson2.c:
TRUE,// HpetMsiDis
FWIW, I hardcoded the above to FA
Michal Zygowski:
>
> On 03.07.2019 04:30, awokd via coreboot wrote:
>> Michal Zygowski:
>>>
>>> On 01.07.2019 14:53, Andriy Gapon wrote:
>>
>>>> It appears that HPET MSI support
>>>> is disabled on some platforms by default:
>&g
Rafael Send:
Hi,
I'm running a Tianocore payload on coreboot and I'm not able to boot
Windows (or Windows installers). I eventually get errors like
"UNMOUNTABLE_BOOT_VOLUME" and "DRIVER_PNP_WATCHDOG".
Some searching leads me to the conclusion that in some cases putting one's
SATA controller in I
duc...@disroot.org:
> Hi,
> Does flashing coreboot/tianocore payload change the settings options
> available in the BIOS setup of a device? I'm talking about the
> device/hardware config options (e.g. enable/disable Secure Boot,
> enable/disable hardware devices etc.) that can be accessed pre-boot
duc...@disroot.org:
> Hi,
> So what I'm hearing is: some configuration settings must be hard-coded during
> compile, and others can be freely configured post-flash using a payload. Is
> that a fair way to look at it?
>
> September 6, 2019 10:26 AM, "awokd via co
bogdal.grzeg...@tutanota.com:
> Hello,
> is there a known solution to my problem?
> After flashing the coreboot and booting the computer, I can use the
> integrated GPU through VGA, but initialization of amdgpu fails and
> DisplayPort external GPU isn't recognized by the system. It appears in lsp
Grzegorz Bogdał:
> Thank you. I'll check it out and report sometime in September whether the
> patches helped my case.
Please note, AFAIK they have only been tested on G505s's, so may need
some modification for your platform.
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Patrick Georgi via coreboot:
> Hi everybody,
>
> coreboot is shipping AMD's open sourced AGESA for a few generations
> as part of its tree.
>
> Some people advocate dropping the code due to its quality and lack
> of maintenance while others are happy with using the code.
>
> So: to help keep thi
Jacob Garber:
> The Coverity issue tracker has several IDE-like features, such as a usage
> finder and go-to definitions. This was adequate for most of my needs, and
> anything else I tracked down using vim and judicious use of grep. There are
> probably more efficient ways to do this (eg. ctags?)
Patrick Georgi via coreboot:
>
> [snip well-written description of contributor/maintainer duties]
Thank you for that. Wonder if it should be added to the project
documentation somewhere- I'd seen bits and pieces of it before on this
list, but it is a great overview.
> Plus, I mentioned it alread
Kyösti Mälkki:
> Preferably fix FSP and not allow this PCI hide-and-seek.
Only for my own education, is that related to
https://www.spinics.net/lists/kernel/msg2709360.html?
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Martin Roth via coreboot:
> - The ONLY platform that supports AGESA f12h is torpedo, and it's
> never been tested, so I'd like to suggest again that it get dropped.
I am seeing some unique Coverity issues in f12h as well. Is there an
established procedure for dropping platforms, or is it as simpl
halilibrahim.rama...@bmc.com.tr:
> hi everyone,
> I'm a beginner of coreboot. I need to know where should i start. Actually i
> follow some steps mentioned here :
> "https://doc.coreboot.org/tutorial/part1.html";. And i made it. after all a
> coreboot.rom file prepared according to my board that
Michal Zygowski:
>
> I will soon update my patches with C_ENVIRONMENT_BOOTBLOCK for binaryPI
> which will be rebased on top of postcar patches (easier for CAR teardown).
Does https://review.coreboot.org/c/coreboot/+/36914 also address
C_ENVIRONMENT_BOOTBLOCK for classic AGESA? Besides Coverity
Could a Coreboot Coverity admin please re-run the scan against master?
Looks like the last analyzed version was from Sep 24, 2019. I would like
to see what AGESA issues remain.
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Patrick Georgi via coreboot:
> On Sun, Nov 24, 2019 at 11:00:00AM +0000, awokd via coreboot wrote:
>> Could a Coreboot Coverity admin please re-run the scan against master?
> Done.
Thank you, but could you please kick Coverity again? Last scan Nov. 26.
Also, I've seen some
Could someone with a Fam16 using integrated graphics test
https://review.coreboot.org/c/coreboot/+/38056 and comment there whether
it worked (still boots and display still shows)?
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Am attempting to resolve one of the last listed High Impact Outstanding
AGESA Coverity issues (1376956), but am struggling to determine the
programmer's intent. In
/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c
line 236, Coverity complains about the 12 element MmioRange array
王一凡:
> Please guys repair coreboot to support my laptop motherboard.
> https://github.com/coreboot/coreboot/pull/18
Please see
https://www.coreboot.org/FAQ#Will_coreboot_work_on_my_machine.3F :
"If your board is not already supported, it will likely take you years
of work to port coreboot to oper
Mike Banon:
> If you know, please tell the AGESA versions of fam15h/fam16h AMD
> vendorcode. For fam14h it is v1.103 - so no questions - but for fam15h
> and fam16h it says v0.001: #define AGESA_VERSION_STRING {'V', '0',
> '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
>From hacking on the cod
Sergej Ivanov:
> I can reproduce this bug on Biostar AM1ML. I think this bug is ACPI
> related, if i add 'nosmp acpi=off' Ubuntu boots fine.
>
> чт, 16 янв. 2020 г., 15:23 Paul Menzel :
>> It’d be great, if you could test this on your coreboot boards, and report
>> back. Adding `nosmp` to the Lin
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