Hi,
I am trying to add a mainboard using celeron J1900 to coreboot-4.14, the serial
console output stops after entering the MRC. The mrc.bin I used is extracted
from Mrchromebox's roms for baytrail based chromebooks.
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Now the raminit passed, thank you very much.
On Thu, 4 Nov 2021 08:56:49 +
Simon Newton wrote:
> Hi there
> Yes it does. Rename mrc.bin to mrc.elf
>
> Regards
>
>
>
> On Thu, 4 Nov 2021 at 08:45, Zhiwen Zheng wrote:
>
> > Hi,
> >
> > I am
<< 7));
On Thu, 04 Nov 2021 10:21:19 +0000 (UTC)
Zhiwen Zheng wrote:
> Now the raminit passed, thank you very much.
>
> On Thu, 4 Nov 2021 08:56:49 +
> Simon Newton wrote:
>
> > Hi there
> > Yes it does. Rename mrc.bin to mrc.elf
> >
> > Regard
I add the following code to sc_init() in southcluster.c to enable SERIRQ, and
it works as expected when doing cold boot. With SERIRQ enabled, the uart in
superio can function correctly, and I can login into the linux serial console.
But after a reboot initiated from linux cmdline, the linux boot
ave similar implementation on braswell, so as long as sc_init get
> executed in ramstage the serial irq mode programming shall be working.
>
> Zhiwen Zheng 于2021年11月6日周六 下午6:29写道：
>
> > I add the following code to sc_init() in southcluster.c to enable SERIRQ,
> > and it w
9oOnKn4hExV-2FWbSoIC1hox-2BZ4-2B0KG0N5l-2BurrwvZ-2FUkvQYEMwmNTgsNqPB6SzAT4IrETNX1EIYiQNwEq5zh02K9uKWvS2Aziixg3mHLtGWAwizUW3YuNDTcGW7B8Vx6biZKem35D86EOq0SDpICxS-2BZDYtiPnDFxRjD9g-3D-3D
> > Have similar implementation on braswell, so as long as sc_init get
> > executed in ramstage the serial irq mode programming shall be working.
> >
> > Zhiwen Zheng 于
-2BCATfg8F03n6hRRS2ALwig078oKTn98eD3mF3Nc4exuyMJHuj8HL7ofdtZVNmKCRPZMP4f4iftjmAtZ5uqmqkFdpVYLpOPb8A-3D-3D
solve the problem.
SMbus also works.
On Mon, 08 Nov 2021 08:54:39 + (UTC)
Zhiwen Zheng wrote:
> I just looked at the patch, it does not reenable continuous mode in ramstage.
> So what I
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