Hello Coreboot Developers,
Display port which comes along with Integrated LVDS, does not show up
any OS graphics display text or screen after booting to OS, the DP port
looks good
during BIOS, at some point of time during OS booting display port turns off
and no
video on DP.
Using ubuntu 18.04
S
Hi Coreboot Team,
There is an external Monitor which works on HDMI/DVI and also DP , In BIOS
the display is good whereas in OS (Ubuntu 18.04) until the kernel is
initialized and i915 Video driver
is loaded display is perfect, looks like the i915 OS driver switches off
the monitor and there is no s
behavior with display port?
HDMI, LVDS, DVI all works well
Thanks
Rao
On Tue, Mar 2, 2021 at 3:29 PM Mike Banon wrote:
> Is your platform coreboot-supported, if yes - have you tested it with
> coreboot?
>
> On Thu, Feb 25, 2021 at 9:09 PM Rao G wrote:
> >
> > Hi Coreboo
You can extract the VBIOS.rom after booting to OS, incase it is linux
echo 1 > /sys/devices/pci:00/:00:02.0/rom cat
/sys/devices/pci:00/:00:02.0/rom > vbios.dump echo 0 >
/sys/devices/pci:00/:00:02.0/rom
the .rom file can be opened with Intel BMP tool
On Tue, Jun 8, 2021
Hi All,
Hope you are doing well.
Platform Baytrail
Issue: Graphics External Display
VBIOS/VBT data
trying to see the MMIO or VBIOS data when a external display device is
plugged/unplugged with DP/HDMI interface, which MMIO register is set or
cleared
Any inputs are appreciated, some of the regi
e is no external display, the VBIOS is causing
delay, so I want to disable PortC for eDP at runtime when there is no
external display connected.
So am trying to find which MMIO register gets set when there is external
Display connected to DisplayPort
Thanks
Rao
On Fri, Jul 30, 2021 at 3:29 PM R
Rao
On Fri, Jul 30, 2021 at 4:49 PM Nico Huber wrote:
> Hi,
>
> On 30.07.21 16:47, Rao G wrote:
> > The problem originally I had was that on PortC, DP/HDMI did not work for
> > the external display in the OS, In BIOS it looked good,
> > so I configured PortC as an
Can this issue be fixed with VBE data configured through BMP or it needs a
fix from graphics MMIO?
Regards
Rao
On Fri, Jul 30, 2021 at 10:27 PM Nico Huber wrote:
> On 30.07.21 18:59, Rao G wrote:
> > Thanks Nico.
> >
> > HPD is active , measured the signal
>
> Is your core
11, 2021 at 3:28 PM Matt DeVillier
wrote:
> On Wed, Aug 11, 2021 at 5:05 AM Rao G wrote:
> >
> > Thanks Nico for your response.
> >
> > > am expecting some register should set with eDP as interface and when
> > > display is connected
> > >
> >
MBOX3 MBox3; // Mailbox 3: BIOS/Driver Communication
INTEL_IGD_OPREGION_VBTVBT; // Video BIOS Table (OEM customizable data)
Regards
Rao
On Thu, Aug 12, 2021 at 10:24 AM Rao G wrote:
> Thank you Matt.
>
> the VBT data in BIOS and VBT data captured in OS if they remain identica
Hi Patrick,
That's good to hear, would there be change to "make menuconfig" with
kconfiglib
Thanks
Ranga
On Wed, Sep 29, 2021 at 10:58 AM Patrick Georgi via coreboot <
coreboot@coreboot.org> wrote:
> Hi everybody,
>
> Historically, coreboot avoided depending on python too much (we got rid of
>
Hi Coreboot Developers,
Very warm greetings!
Trying to enable PXE along with UEFI payload on Elkhart Lake CRB platform
Enabling Network stack requires below DXE drivers to be enabled
https://github.com/tianocore/edk2/blob/vUDK2018/MdeModulePkg/MdeModulePkg.dsc
MdeModulePkg/Universal/Networ
Hi All,
Trying to enable GPU clock throttling on Intel Gen 7 UHD
The SoC is E3815 Atom BayTrail
On Ubuntu
*command*
*i*ntel_gpu_frequency
*output*
cur:200MHz
min:200MHz
RP1:400MHz
max:400 MHz
Can GPU Frequency be throttled? Any specific registers to enable throttling
for GPU/GFX
Thanks
Ranga
Hi All,
Any clues on GPU throttling?
BR's
Ranga
On Thu, Oct 21, 2021 at 2:42 PM Rao G wrote:
> Hi All,
>
> Trying to enable GPU clock throttling on Intel Gen 7 UHD
>
> The SoC is E3815 Atom BayTrail
>
> On Ubuntu
>
> *command*
> *i*ntel_gpu_frequency
>
Hi Coreboot Team,
Am trying flashrom 1.2 on W25R256JVEIQ NOR flash. Datasheet below
https://www.mouser.ie/datasheet/2/949/Winbond_Electronics_Corporation_11012018_W25R256JV-1499901.pdf
Flashrom supports below winbond DEVID's but not W25R series?
In Ubuntu /sys/class/mtd0 does not exist error is
Hi All,
Trying to figure out how the GOP driver is enabled/added in the coreboot
tree.
IntelGraphicsPeim.efi
IntelGopDriver.efi
Above 2 drivers part of FSP?
Intel is providing DisCon tool to configure VBT, this tool is a replacement
for BMP which is EOL
Thanks for your time!
Best Regards
Rang
Thanks Michal for your response.
On Thu, Dec 2, 2021 at 2:08 PM Michał Żygowski
wrote:
> Hi Ranga,
> >
> > Trying to figure out how the GOP driver is enabled/added in the coreboot
> > tree.
> >
> > IntelGraphicsPeim.efi
> > IntelGopDriver.efi
> >
> > Above 2 drivers part of FSP?
>
> IntelGraphi
Hi All,
Good morning!
EFI Payload in coreboot has enabled
MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
in .dsc/.fdf file
There is a *SerialRead *function in this DXE Driver, am trying to access F2
from UART Console
but this does not work, How to enable this feature?
Who is invoking Seria
Hi All,
Trying to access SPI Flash from EFI payload
1)
SpiInstance->PchSpiBase = MmPciBase (
DEFAULT_PCI_BUS_NUMBER_PCH,
PCI_DEVICE_NUMBER_PCH_SPI,
PCI_FUNCTION_NUMBER_PCH_SPI
)
Yes 0xC00FD000 (Bus 0 Dev 1F Func 5) not Func 0
Thanks
Rao
On Fri, Jan 28, 2022 at 3:40 PM Jeff Daly wrote:
> 0xFD000 is bdf 0/1f/5, not 0/1f/0
>
> Is your SPI controller at function 5?That’s where it usually is for
> Intel SoCs.
>
>
>
> *From:* Rao G
> *Sent:*
That's correct, PCIE_BASE= 0xC000
On Fri, Jan 28, 2022 at 4:32 PM Jeff Daly wrote:
> And your ECAM base address for PCIE is at 0xC000 ?
>
>
>
> *From:* Rao G
> *Sent:* Friday, January 28, 2022 11:21 AM
> *To:* Jeff Daly ; coreboot
> *Su
gt; links or opening attachments.
>
>
>
> That's correct, PCIE_BASE= 0xC000
>
>
>
> On Fri, Jan 28, 2022 at 4:32 PM Jeff Daly wrote:
>
> And your ECAM base address for PCIE is at 0xC000 ?
>
>
>
> *From:* Rao G
> *Sent:* Friday,
Hi All,
Trying to pass data between EFI Payload and coreboot, my use case is
when a setup token is enabled, the data should be read by coreboot and
change the DEBUG options in coreboot
In EFI Payload values in PcdDebugPropertyMask can be toggled to ON/OFFit
Please shed some light onto it
Thanks
Hi All,
On elkhartlake_crb
https://github.com/coreboot/coreboot/blob/master/src/mainboard/intel/elkhartlake_crb/romstage_fsp_params.c
ehlcrb_spd_info.read_type = READ_SPD_CBFS;
ehlcrb_spd_info.spd_spec.spd_index = 0x00;
*Can this setting be changed to READ_SMBUS?*
Seeing Memory Init failures i
Hi All,
Did anybody work on Elkhart Lake that comes with PSE Firmware?
I don't see any devices getting enumerated which are under PSE I2C,UART,
Gbe,TSN
The logs shows
PSE Firmware Status is A138 read from address FE400034
BIOS: PSE FW is loaded and running
Looks like FSP is disabling PSE device
: 0x, Vendor Id: 0x
Thanks
Ranga
Thanks
Ranga
On Thu, Mar 31, 2022 at 3:04 PM Rao G wrote:
> Hi Sheng,
>
> Thanks for your email and response.
>
> 1. Yes I used unsigned binary - PSE_FW that came along with 638228_PSE
>
> 2. In Device Tree
> device pci 1d.0 off
Thanks
Ranga
On Thu, Mar 31, 2022 at 3:19 PM Rao G wrote:
> Hi Sheng,
>
> In the coreboot log I see
>
> PCI: 00:1d.0 [8086/4bb3] disabled
> PCI: Static device PCI: 00:1d.1 not found, disabling it.
> PCI: Static device PCI: 00:1d.2 not found, disabling it.
>
>
Hi Everyone,
On the Baytrail platform with ALC262 Realtek Codec, HDA Audio is enumerated
as PCI device 00 1b 00,
the verb table is being programmed on HDABAR + command offset.
Using uefi Payload which has PchInit -> DetectAndInitializeAzalia, there
are no Errors in this path, all looks good
Eith
,
revision = 0x0.
SDI3 has no Azalia device.
ConfigureAzalia() End
AzaliaEnable = 1
On Mon, Dec 28, 2020 at 11:57 AM Paul Menzel wrote:
> Dear Ranga,
>
>
> Am 28.12.20 um 12:45 schrieb Rao G:
>
> > On the Baytrail platform with ALC262 Realtek Codec, HDA Audio is
> enumerated
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