[coreboot] DIP8 flash programming for development

Hi, I'm thinking about porting coreboot to a FM2A88X Extreme4+ board. This board has a DIP8 flash with a socket and I wondered what would be the best way to do an efficient development cycle. Ideally, I suppose that the best option would be to use a clip test and a CH341A, but all the clips that I

[coreboot] POST codes and PCI Post card

I've noticed that POST codes are sent very early. In x86 the first code is sent just after storing the bist. Are codes sent so early useful? They are sent ages before any PCI configuration. Is there any guarantee of them reaching a PCI POST card? ___ core

[coreboot] Image size and cpu-flash addresses.

Hi everyone, I was going to try coreboot on an ASROCK FM2A88X Extreme4+ ( https://www.asrock.com/mb/AMD/FM2A88X%20Extreme4+/) with the configuration of the supported ASUS A88XM-E ( https://doc.coreboot.org/mainboard/asus/a88xm-e.html) which has the same chipset (A88X Bolton). The fact is that, at

[coreboot] Stuck on SB clock to SIO.

Hi everyone. I'm a bit stuck on this. As I've said before in other emails here, I'm trying to bring up an AsRock FM2A88X+ with coreboot. I've used as a model the code for the a88xm-e and accomplished my first goal, which was to have a working UART, but I need to boot with the original AMI BIOS fi