Re: [coreboot] Creating patches

On 20.08.2011 12:10, Paul Menzel wrote: Then send them in using Gerrit [1][2] or use git format-patch -2 # number can be and use `git send-email` to send them in for review to the list. Mails posted to the list don't end up on Gerrit. Given that Gerrit is the gatekeeper, you better pus

[coreboot] FILO managed by Gerrit and Jenkins now, also coreboot patchwork status

Hi, just a small heads-up (well, two): FILO is now managed by Gerrit, using Jenkins for build-testing it. It uses the latest libpayload of coreboot to validate that things work. I also cleaned out coreboot's patchwork instance some more - we now have less than 200 "unhandled" patches there,

Re: [coreboot] [PATCH] Adding Jetway J7BXAN to mainboards list

On Mon, 5 Sep 2011 20:16:09 +0530 (IST), Abhinav Hardikar wrote: I have posted the video of coreboot working on the mobo. Now I am sending this working patch. I have tested it. Could you please submit it to our Gerrit instance? See http://www.coreboot.org/Git for instructions. Thanks, Patrick

Re: [coreboot] FILO managed by Gerrit and Jenkins now, also coreboot patchwork status

On Tue, 6 Sep 2011 11:21:39 +0300, Tadas Slotkus wrote: Hi, I would prefer that patch mails have a [FILO] tag instead of [coreboot]. That tag is created by the mailing list handler itself. I guess I could enhance the mail template a bit, to add the project name at appropriate places ("patch add

Re: [coreboot] barbarians at the gates

Am 09.09.2011 15:22, schrieb Peter Schmidt: seems like more and more dongle-functionality is going into UEFI: http://www.h-online.com/security/news/item/Windows-8-to-include-secure-boot-using-UEFI-2-3-1-1335246.html http://vr-zone.com/articles/the-upgrade-path-to-ivy-bridge-might-be-blocked-by-c

Re: [coreboot] barbarians at the gates

Am Mo 12 Sep 2011 13:06:07 CEST schrieb Peter Schmidt: Coreboot is the alternative to UEFI. It's complementary. UEFI (or what the consumer understands by it) barely covers hardware initialization, while coreboot doesn't really concern itself with firmware APIs. With Linux there are already p

Re: [coreboot] I am reading the source code of coreboot, how do I understand the functions

Am Mo 12 Sep 2011 17:48:07 CEST schrieb Jianmin Pan: I am used to use vim. So, anybody have good suggestions? Install ctags, run "ctags -R src" in the toplevel directory, which creates the "tags" file. Then in vi, use ":ta identifier" to look up the declaration of identifier, ctrl-] to look u

Re: [coreboot] DL145 G1 with dual dualcore CPU using coreboot ?

Am 22.09.2011 12:53, schrieb Oskar Enoksson: Checking out and compiling the latest git-version of coreboot yields no output whatsoever on the serial console. Something is definitely very broken and there is no clue. It's possible that things are _very_ slow. This sometimes happens if printk is

Re: [coreboot] DL145 G1 with dual dualcore CPU using coreboot ?

Am Freitag, 23. September 2011 01:45:09 schrieb Oskar Enoksson: > As for the "dead" behaviour in recent versions I bisected my way down > to commit 1f7d3c5672ec90f8d71907b1a07c8a87fa461047 (svn 6124). That > commit adds "TINY_BOOTBLOCK support" to AMD-8111 southbridge. I > understand that this com

Re: [coreboot] #181: Tyan S2885 (and other K8 boards) won't boot with TINY_BOOTBLOCK

Am Do 29 Sep 2011 09:59:27 CEST schrieb Kent Hagebrand: Will do asap. Don't see any patching for my board in: src/mainboard/asus/a8n_e/romstage.c isn't that also needed? It should work without any patch to the romstage (I think), but please try with the enumerate_ht_chain() call in romstage.c re

Re: [coreboot] how to delete symbol link created at compile time

Am Donnerstag, den 13.10.2011, 17:19 +0800 schrieb She, Kerry: > I have created 2 devicetree file : > > devicetree_f15.cb for platform with family 15 CPU > devicetree_f10.cb for platform with family 10 CPU What are the differences exactly? If possible, I'd like to look for a solution that allow

Re: [coreboot] Gerrit config (was: Re: Patch merged into coreboot/master: 7f8e685 Load an IDT with NULL limit)

Am Freitag, den 14.10.2011, 01:32 +0200 schrieb Uwe Hermann: > On Thu, Oct 13, 2011 at 08:04:27PM +0200, ger...@coreboot.org wrote: > > the following patch was just integrated into master: > > commit 7f8e685996f65f2c67d1113fcfaab33ccc385da7 > > Author: Stefan Reinauer > > Date: Wed Jun 1 14:01:4

Re: [coreboot] Gerrit config (was: Re: Patch merged into coreboot/master: 7f8e685 Load an IDT with NULL limit)

Am Freitag, den 14.10.2011, 01:32 +0200 schrieb Uwe Hermann: > Can gerrit be configured to show > > - who approved a patch and when I implemented this (but didn't add it to the hook yet): Reviewed-By: Patrick Georgi at Fri Oct 14 08:11:24 2011, giving +2 Build-Tested: build bo

Re: [coreboot] How to make "System Restart after Power Fail" working onSB800?

Am Mo 17 Okt 2011 03:24:53 CEST schrieb mopz0506 mopz0506: coreboot is really really too hard for those users who just want to run a NAS / BT server in his/her living room. That's because the kind of problems that coreboot solves are hard without some knowledge about the inner workings of comp

Re: [coreboot] Intel SCH CMC(Chipset Microcode) state machine binary?

p://www.coreboot.org/pipermail/coreboot/2011-March/064246.html See http://review.coreboot.org/305 Regards, Patrick -- Patrick Georgi SINA-Development - High Security secunet Security Networks AG - Mergenthalerallee 77 - 65760 Eschborn, Germany Phone +49 201 54 54-3610 - Fax +49 201 54 54-1325 - w

[coreboot] [RFC]What to do with TINY_BOOTBLOCK?

Hi all, as you may be aware, coreboot has two different ROM layouts so far. The older one is derived from what we did before CBFS, and has all code that does RAM init (our "romstage") in the bootblock (up to 64k at the top end of the image). This worked for a long time, but required some hack

Re: [coreboot] [RFC]What to do with TINY_BOOTBLOCK?

Am Montag, 24. Oktober 2011 21:53:24 schrieb Marc Jones: On Mon, Oct 24, 2011 at 12:37 PM, Kyösti Mälkki wrote: On Mon, 2011-10-24 at 10:22 -0600, Marc Jones wrote: On Mon, Oct 24, 2011 at 4:15 AM, Patrick Georgi wrote: Hi all, as you may be aware, coreboot has two different ROM layouts so

Re: [coreboot] [RFC]What to do with TINY_BOOTBLOCK?

On Mon, 24 Oct 2011 18:06:54 -0700, Stefan Reinauer wrote: We create an deprecated_boards_201110 branch which holds e.g. all romcc boards, and drop them from the most current tree. If we go down this road, the tree easily shrinks to the 20-or-so boards that are actually in use/worked on. Maybe

Re: [coreboot] Trouble with cbfstool when attempting dualboot

Am Fr 28 Okt 2011 07:18:36 CEST schrieb Kyösti Mälkki: I have trouble making dual fallback/normal image. [detailed report] Any thoughts? The change in http://review.coreboot.org/351 should fix it Thank you for the report. Patrick -- coreboot mailing list: coreboot@coreboot.org http://www.core

Re: [coreboot] jenkins fails on 3aade48 on unrelated file (was Re: Change in coreboot[master]: w83627hf: drop Scope(\_SB) from ASL include)

Am 30.10.2011 19:27, schrieb Christoph Grenz: > jenkins log: >> CC cpu/amd/model_10xxx/processor_name.ramstage.o >> src/southbridge/amd/sr5650/pcie.c: In function 'sr5650_gpp_sb_init': >> src/southbridge/amd/sr5650/pcie.c:377:19: error: 'slave_cpl' may be used >> uninitialized in this f

Re: [coreboot] Trouble with cbfstool when attempting dualboot

Am Montag, 31. Oktober 2011 07:32:50 schrieb Kyösti Mälkki: If my new normal/romstage is built with GCC for Cache-As-Ram, the same alignment does not apply and on boot it halts before any serial output. Does it "halt" or is it just _very_ slow (several minutes until the first life sign on serial

Re: [coreboot] Trouble with cbfstool when attempting dualboot

Am 01.11.2011 14:02, schrieb Kyösti Mälkki: My Cache-As-Ram boot enters intel/car/cache_as_ram.inc but never reaches LogicalAP_SIPINotdone in it. I found a note in this file saying LAPIC ID logic works only for processors with two threads, so does a dual Xeon P4/HT setup require re-writing this l

Re: [coreboot] Patch set updated for coreboot: 7849219 Update coreboot cross toolchain to gcc 4.6.1

Am 29.10.2011 22:34, schrieb Nils: CC wasn't set and bison and flex were not instaled. The acpica-unix-20110922/README states that the Makefiles contain CC = gcc but only the main acpica-unix-20110922/generate/ unix/Makefile.config contains it and it is not used by coreboot. We better pass CC in

Re: [coreboot] buildgcc broken

Am Sa 05 Nov 2011 20:16:01 CET schrieb Nils: I tried to test Patricks new patch "Change Id9e6b204: buildgcc: Explicitely state CC everywhere" but crossgcc doesn't compile at al. The problem started after commit: "Change I1b7d5b89: buildgcc: Update coreboot reference toolchain to gcc 4.6.2" The

Re: [coreboot] [RFC] A more robust fallback system

Hello Noé, first, welcome to the coreboot community! Am 15.11.2011 12:07, schrieb Noé Rubinstein: system, by putting a 'fallback' Coreboot in the high, write-blocked part of the boot ROM, and using the fallback mechanism already implemented in Coreboot in order to fallback in case the user-flas

Re: [coreboot] [RFC] A more robust fallback system

Am 15.11.2011 23:42, schrieb Guillaume Knispel: We can't put the fallback at the beginning of the image because that area can't be locked on the chip we are using. (SST25VF016B) Thanks! That was the missing part in your scenario. Most current chips support sector granularity (usually 4kb, someti

Re: [coreboot] Patch set updated for coreboot: 6709bdd Fix multipleVGA cards resource conflict on Windows

Am 19.12.2011 18:02, schrieb ron minnich: > I wonder if a better way to manage this is via a CMOS (aka NVRAM) > setting. No user visible configuration if it can be avoided, please. > I kind of hate to limit coreboot because Windows is limited. > But I'm a n00b in a sense, having just come back on

Re: [coreboot] gerrit/jenkis missing builds.

Am 21.12.2011 03:28, schrieb Marc Jones: > It looks like these patches didn't get built by jenkins. Thanks for the notice. > http://review.coreboot.org/#change,487 > http://review.coreboot.org/#change,488 I triggered these manually and will have to look into what happened there originally. > http

Re: [coreboot] gerrit/jenkis missing builds.

Am 21.12.2011 18:55, schrieb Marc Jones: > What is a difference between Jenkis setting a -1 "unstable" vs a "red > x" in verified? "verified -1" is when any build fails "unstable" is when the builds report success but the test harness reports issues. unstable will only happen for us when messing a

Re: [coreboot] New patch to review for coreboot: db051bf Fix missing VM mapping

Am 24.12.2011 05:16, schrieb ron minnich: > I'm just getting back to coreboot. Is libpayload used verbatim in the > kernel? The phys/virt map in coreboot is 1:1 by design. The mapping > seems unnecessary to me. Just wondering. libpayload provides phys/virt mapping because FILO relocates itself to h

Re: [coreboot] tiny bootblock problem

Am 27.12.2011 23:21, schrieb Nils: Is that a caching problem introduced by tiny bootblock? What is needed to get it right? Probably MTRRs. With tinybootblock, these are set at slightly different times. GX2 uses Cache-As-RAM, right? That affects MTRRs, too (as CAR is a "special" MTRR setup) P

Re: [coreboot] tiny bootblock problem

Am 06.01.2012 19:43, schrieb Nils: Correct me if i'm wrong but Geode GX2/LX doesn't have MTRRs. Cache is setup via MSR registers. MTRR is usually configured via MSR (0x200 to 0x210, specifically). Not sure if Geode does it the same way, but MSR doesn't mean "no MTRR". Patrick -- coreboot mai

Re: [coreboot] How to port core boot

Am 05.02.2012 13:50, schrieb ali hagigat: > My motherboard is Pentium III, Intel 82815 and ICH2. I want to port > the Coreboot to this motherboard and I already have an assembly > routine which initializes the RAM modules. Where is that assembly routine from? Regards, Patrick -- coreboot mailin

Re: [coreboot] libpayload alloc() gcc 4.6.2 bug?

Am 28.02.2012 23:06, schrieb Marc Jones: > I found this bug building tint with libpayload. libpayload is built > with defconfig and using the same coreboot crosstools gcc. The bug > happens in the first call to alloc() when the first header of the > first region is installed. The header memory loca

Re: [coreboot] A bit of help needed

Am 10.03.2012 11:49, schrieb Jaspal Dhillon: > I was going through the coreboot.org and I am > definitely interested in it. Welcome to coreboot, then! > So wanted to ask couple of things. > I have not read the source code yet but tried it out in this way : > 1.Checked out la

[coreboot] separate mailling list for gerrit mails?

Hi, this came up on IRC again, but I think the issue requires wider discussion: Several people asked if gerrit mails can be moved to a separate mailing list to reduce the "mechanic" noise. We're highly flexible there, so we can keep it like it is, reduce the number of mail types, send different t

Re: [coreboot] [RFC] Improve very early boot

Am 15.03.2012 15:00, schrieb Kyösti Mälkki: > On selected boards, some hardware initialisation is placed in the > bootblock. The source files and directories are currently hard-coded in > Kconfigs, which is sort of ugly. > > A few months ago I put together changeset [1], which hasn't drawn much >

Re: [coreboot] Coreboot overwrites seabios .config at build time

Am 18.03.2012 06:45, schrieb HighlyCaffeinated: > If any options are changed in Seabios - either via direct editing of > the .config file or by 'make menuconfig' in the build/seabios > directory, those changes are overwritten by coreboot during before > it begins the seabios build. How can this b

Re: [coreboot] Can we push using http user/password authentication

Am 23.03.2012 11:27, schrieb Bao, Zheng: > Hi, > Actually, I have done all the settings, including http password. > After I run git push, it says, > > Counting objects: 5, done. > Delta compression using up to 4 threads. > Compressing objects: 100% (3/3), done. > Writing objects: 100% (3/3), 480 b

Re: [coreboot] separate mailling list for gerrit mails?

Am 12.03.2012 09:55, schrieb Mathias Krause: > For me the annoying thing is that gerrit is not fully integrated into > the mailing list and vice versa, too. Review done on the gerrit web page > is not mirrored to the mailing list and reviews done on the mailing list > gerrit will not be aware of. S

Re: [coreboot] New patch to review for coreboot: c2e50ec Use fast memset in SMM mode, too

Am 04.04.2012 19:51, schrieb Peter Stuge: > Stefan Reinauer wrote: >> ... and always include IP checksumming in romstage. It's generally >> useful and our upcoming port needs it. > I don't know.. Why add code which in most cases isn't being used. > We've created a fairly elaborate and powerful bui

Re: [coreboot] Patch merged into coreboot/master: c35c461 Invalidate cache before first jump

Am 06.04.2012 17:27, schrieb Marc Jones: > Can you be more descriptive to how it fails? Does it hang on that > instruction? That change might also break on future CPUs (if they finally manage to make the TPM stuff secure, so that's a big if) Patrick -- coreboot mailing list: coreboot@coreboot.o

Re: [coreboot] Patch merged into coreboot/master: c35c461 Invalidate cache before first jump

Am 06.04.2012 20:26, schrieb Stefan Reinauer: >> That change might also break on future CPUs (if they finally manage >> to make the TPM stuff secure, so that's a big if) > How so? Load top x KB into cache, let the CPU measure the data from cache into a PCR, run the code from cache (to avoid TOCTOU

Re: [coreboot] [RFC] Re-thinking the stages

Am 06.04.2012 20:12, schrieb Marc Jones: > There is a lot of assumed configuration ownership in the vendor code, > and coreboot may need to adjust to that. Something else to consider as > you design these stages. Reminds me: can we get rid of platform_cfg.h on AGESA boards, please? Patrick -- c

[coreboot] [updated PATCH] Re: [cbv2]Add serial port information to lbtable

ne in a compatible way, or not? I'll do patches for lxbios and v3 once this patch (and more importantly, the record format) is accepted. This patch is updated against latest svn, and provides an alternative in case TTYS0_BASE isn't defined (see the #ifdef). Regards, Patrick Georgi Th

Re: [coreboot] [cbv2]Add serial port information to lbtable

y taken in v3, so 0xe must be changed (just for reference). I'll post another patch, with a new ID (a v3 patch exists and works already, that'll come, too) and work on a proposal for LB_TAG_CONSOLE - tomorrow. Regards, Patrick Georgi -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [cbv2]Add serial port information to lbtable

gt; like the generic serial tag. Attached patch changes the following vs. the version as of yesterday: - fix comment (patch adds a serial port, not a console) - change tag ID to 0xf (0xe is already taken in v3) Regards, Patrick Georgi This patch adds a new record type for lbtable to provide info

Re: [coreboot] [cbv2]Add serial port information to lbtable

dded (somehow) on an as-needed basis. No need in designing a one-size-fits-all solution when it might not fit actual usage later on. Regards, Patrick Georgi -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] [RFC] consoles, serial ports and all that for v2 and v3 payloads

ade when there's an actual use case, thereby reducing the problem space right now. I'd like to go on with that, and will do so in a few days. Please don't wait until I have a patch ready for all that stuff, before telling me it's crap ;-) So... Comments? :-) Regards, Patrick Georgi

Re: [coreboot] rename LAR to CBAR and LBTABLE to CBTABLE?

mpossible to tell CorebootARchiver and CacheAsRam apart. How about renaming LAR to "lightweight archive(r)" and keep the short name? Regards, Patrick Georgi -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] Rename lxbios to nvramtool

Am Freitag, den 25.01.2008, 16:37 +0100 schrieb Uwe Hermann: > If I get an ACK for the patch, I'll do steps 2 and 3 also, right after > comitting the patch. How does that interact with those "symbolic links" in the cbv2 and cbv3 trees? Regards, Patrick Georgi --

Re: [coreboot] [RFC] consoles, serial ports and all that for v2 and v3 payloads

cessary won't work > Extending/splitting the info about > the console in use into a config and a device part allows extensions for > those devs that are slow to probe, IDE disks in particular. See above: device part != config (in this case: console) part. > If we agree that prob

[coreboot] [PATCH][v2] buildtarget tries to apply make syntax to shell

Hi, see attached patch Regards, Patrick Georgi bsh/ksh-clone and make(1)-syntax don't go well together (unlike 5 lines later where make syntax is emitted into a file) Signed-off-by: Patrick Georgi <[EMAIL PROTECTED]> Index: targets/

[coreboot] [PATCH][v2]Consoles in lbtable

h 20 values of which usually only the 5 (that apply to this specific device) are used. Regards, Patrick Georgi Add a new record type "console" for lbtable, and insert one record for each output device we support, so the payload can figure out where to find consoles that the user cares

Re: [coreboot] [PATCH][v2]Consoles in lbtable

Am Samstag, den 26.01.2008, 21:31 +0100 schrieb Stefan Reinauer: > Is there a reason you are hardcoding the type here, despite > passing one in add_console? ;-) doh, thanks.. what about the types of console - should I keep them all? Regards, Patrick Georgi -- coreboot mailin

Re: [coreboot] LinuxTag 2008 in Berlin, May 28-31

hat it would take to do > this, I just think it would be cool. Comments? There's a java based x86 emulator, that could be used: http://www-jpc.physics.ox.ac.uk/ But I have no idea how accurate it is in early initialization. Regards, Patrick Georgi -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] LinuxTag 2008 in Berlin, May 28-31

Am Sonntag, den 27.01.2008, 14:11 +0100 schrieb Patrick Georgi: > Am Sonntag, den 27.01.2008, 05:57 -0500 schrieb Corey Osgood: > > A bit off-topic, but this is an idea I've been toying with for a > > little > > while now: a web-based interface to see coreboot in acti

Re: [coreboot] sudo update-grub doesn't change entries in menu.lst (grub 1.95)

gt; > Any ideas, suggestions other than installing grub 0.97 ? > I have the slight feeling you're on the wrong mailing list. [EMAIL PROTECTED] might be a better place for grub support, or use the support channels of your distribution. Regards, Patrick Georgi -- coreboot mailing list cor

Re: [coreboot] [openvsa] Fix for 64 bit hosts and Ubuntu

e programs. I'm proud of them. > As can be seen with the various ld failures popping up again and again, standalone programs are not an official supported scenario for them (except for whatever kernel the system is using) Regards, Patrick Georgi -- coreboot mailing list coreboot@cor

Re: [coreboot] LAR TODO

up in a file "entry", 4 bytes large, containing nothing but the address to jump to. I think, that approach would be even simpler, while still keeping the advantages of your proposal. Regards, Patrick Georgi -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] LAR TODO

Am Dienstag, den 19.02.2008, 16:48 +0100 schrieb Patrick Georgi: > How about doing segments per file (like right now), and simply > prepending their data "section" with the load address (as they already > get special treatment anyway). Follow up to this issue: the first

Re: [coreboot] [PATCH][v3] Argument order in compiler options

Peter Stuge schrieb: > With the below question answered, this is: > > Acked-by: Peter Stuge <[EMAIL PROTECTED]> > Thanks, r690. > HOST_LOADLIB*E*S > > Is that last E a typo? > I think so (and see nothing that indicates otherwise) - I opted for the minimal patch, but I suppose fixing it (if o

[coreboot] [PATCH][v3] read actual memory size in qemu-i386

Hi, the attached patch makes the i440bx emulation read the cmos registers of the bochs/qemu emulation that carry RAM size information instead of assuming 128MB. Regards, Patrick Signed-Off-By: Patrick Georgi <[EMAIL PROTECTED]> Index: northbridge/intel/i440bxemulation/

Re: [coreboot] [PATCH][v3] read actual memory size in qemu-i386

Peter Stuge schrieb: > On Fri, Jun 06, 2008 at 11:01:06PM +0200, Patrick Georgi wrote: > >> -ramsize = "128"; >> > Is this parameter now used anywhere else? > The only other reference for "ramsize" I find is doc/design/newboot.lyx, whic

Re: [coreboot] coreboot and U-Boot: a comparison

ron minnich schrieb: >> 8) U-Boot now has architecture specific git repositories for >> active development available via http protocol that passes >> through most firewalls transparently. coreboot has a >> single SVN repository that seems to be accessible only >> via the svn protocol which

Re: [coreboot] USB debug cables and emulation

Joseph Smith schrieb: > Than you did not read all of it. At the end"I was finally able to get > console output on the iMac" > Yes, by using the default USB controller in polled mode (ie. no IRQ handling). The USB debug port is a different facility. Regards, Patrick -- coreboot mailing list

[coreboot] [PATCHes][v2][v3] baud rate in serial entries in lbtable (and console entries in lbtable for v3)

each patch. Regards, Patrick Georgi Signed-Off-By: Patrick Georgi <[EMAIL PROTECTED]> Index: src/include/boot/coreboot_tables.h === --- src/include/boot/coreboot_tables.h (revision 3393) +++ src/include/boot/coreboot_tables.h (w

[coreboot] [PATCH][v3] read actual memory size in qemu-i386

32) 2. Where to put inb_cmos, which so far is only used in nvramtool, a userspace app. Regards, Patrick Georgi Signed-Off-By: Patrick Georgi <[EMAIL PROTECTED]> Index: northbridge/intel/i440bxemulation/domain === --- northb

Re: [coreboot] [PATCHes][v2][v3] baud rate in serial entries in lbtable (and console entries in lbtable for v3)

Stefan Reinauer schrieb: > Patrick Georgi wrote: > >> Hi, >> >> two patches this time, one for cbv2, one for cbv3: >> >> patch-20080628-1-baud-in-serial-cbv2 >> adds an entry to the serial port descriptor about the configured line >> speed. this

Re: [coreboot] Support to Intel CPUs

issue seems to be that intel is less willing to do that than others, and if they are, they seem to move rather slowly. Regards, Patrick Georgi -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] USB debug cables and emulation

# northbridge works for me) is most of the UHCI stuff, and mass storage. Everything else is pretty much free for grabs (but it might be good to tell me so I don't step on your toes). OHCI and mouse are definitely not on my list for the short term, other usb device drivers also aren't.

Re: [coreboot] SMM handling and resident coreboot

others might consider it. Patrick Georgi -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [libpayload] patch: add cbtables code to libpayload

Sean Nelson schrieb: patch to move coreboot table code into libpayload. Allows payloads using libpayload to access coreboot tables. Signed-Off-By: Sean Nelson <[EMAIL PROTECTED]> What about licensing? libpayload is BSD-licensed, the cbtable code seems to be GPL. Regards, Patrick

[coreboot] Test installation of the review board webapplication

ch of the subprojects, there's a review group that you can subscribe to. This has the effect that you see related review requests in your dashboard (frontpage of the app) and (in later stages) get mail notifications for the projects you're interested in. Comments welcome! Regards, Patrick

Re: [coreboot] [PATCH] v3: optional compilation with -fwhole-program

Carl-Daniel Hailfinger schrieb: > How about UNREASONABLE_OPTIMIZATION? Or OVERBOARD_OPTIMIZATION (although > that can be misunderstood by non-native speakers as referring to a board)? > how about any of: experimental optimization excessive optimization maximum optimization (potentially) unstable

Re: [coreboot] r835 - in coreboot-v3/include: . arch/x86

[EMAIL PROTECTED] schrieb: > Modified: coreboot-v3/include/globalvars.h > === > --- coreboot-v3/include/globalvars.h 2008-08-28 01:57:14 UTC (rev 834) > +++ coreboot-v3/include/globalvars.h 2008-08-28 02:32:27 UTC (rev 835) > @@ -31,

[coreboot] [PATCH]libpayload: memalign, take 2

Hi there, after the discussion on the list about memalign, I wrote version that's better integrated with the other memory management stuff, and doesn't come with its own pool allocator. Regards, Patrick Georgi Signed-off-by: Patrick Georgi <[EMAIL PROTECTED]> Index: incl

Re: [coreboot] [PATCH] libpayload keyboard driver fix.

have no idea why that didn't occur to me when I looked at it earlier today :-/ Acked-by: Patrick Georgi <[EMAIL PROTECTED]> > > >> Signed-off-by: Stefan Reinauer <[EMAIL PROTECTED]> >> >> Index: libpayload/drivers/keyboard.c >> =

Re: [coreboot] libpayload: memalign, take 2

Jordan Crouse schrieb: >> Signed-off-by: Patrick Georgi <[EMAIL PROTECTED]> >> > > Acked-by: Jordan Crouse <[EMAIL PROTECTED]> > Thanks, r3559 -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] libpayload: USB stack

Jordan Crouse schrieb: >> Signed-off-by: Patrick Georgi <[EMAIL PROTECTED]> >> > Acked-by: Jordan Crouse <[EMAIL PROTECTED]> > Thanks, r3560 -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] [PATCH]libpayload: video/vga driver checks unsigned variables for negative values

Hi, attached patch makes cursorx and cursory signed, as there are several "if (cursorx < 0)" tests. I also added another one, to make backspace wrap backwards into the previous line, if necessary. Patrick Georgi === drivers/

Re: [coreboot] [PATCH]libpayload: video/vga driver checks unsigned variables for negative values

Patrick Georgi schrieb: > Hi, > > attached patch makes cursorx and cursory signed, as there are several > "if (cursorx < 0)" tests. > I also added another one, to make backspace wrap backwards into the > previous line, if necessary. > Oops, forgot this: Sig

Re: [coreboot] Convert Assembly JMP to C

t booting from various IDE/SCSI/whatever controllers) Regards, Patrick Georgi -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Automatic drive enumeration

> some code? > > Do we want to consider different architectures at this point already? > If so: bytecode. seriously. Patrick Georgi -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] FILO creating filo.conf

ut I have an idea if I can figure this > out. If a normal bios can save a password (ASCII text) than why couldn't > FILO save a kernel command line (ASCII text)? > I think, they store one or two bytes of hash value in CMOS Regards, Patrick Georgi -- coreboot mailing list:

Re: [coreboot] [PATCH] libpayload/tinycurses keyboard driver fault

Stefan Reinauer schrieb: > See patch > Before someone commits this: the patch below fixes this by removing the code in question altogether, using the generic keyboard driver instead. That one was changed a bit, too, see patch header. Regards, Patrick Georgi - unify keycodes for non-ASCI

Re: [coreboot] [PATCH] libpayload/tinycurses keyboard driver fault

Patrick Georgi schrieb: > Before someone commits this: the patch below fixes this by removing the > code in question altogether, using the generic keyboard driver instead. > That one was changed a bit, too, see patch header Slightly updated, to cursor keys on keyboard work, too. (just som

Re: [coreboot] [PATCH] libpayload/tinycurses keyboard driver fault

Patrick Georgi schrieb: > Slightly updated, to cursor keys on keyboard work, too. (just some > cut-off because of putting a short into a char) > Tested in qemu, both console and serial. > Today's my oops day when it comes to sending patches: some local stuff ended up in there.

[coreboot] [PATCH]filo and libpayload: Support Solaris in kconfig

clude from util/kconfig/zconf.tab.c_shipped. This file includes expr.h already, so it picks up the right set of primitives, without duplicating the special case for Solaris. Comments? Patrick Georgi Signed-off-by: Patrick Georgi <[EMAIL PROTECTED

Re: [coreboot] [PATCH]filo and libpayload: Support Solaris in kconfig

etc? > Probably yes. It can't hurt. Patrick Georgi -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Tinycurses depends on active video console.

Mats Erik Andersson schrieb: Index: libpayload/curses/tinycurses.c === --- libpayload/curses/tinycurses.c (revision 3623) +++ libpayload/curses/tinycurses.c (arbetskopia) @@ -736,8 +736,10 @@ for (x = win->_

Re: [coreboot] splash screen

ron minnich schrieb: > Remember the original linuxbios slogan? "Let Linux do it". > Just that Linux grew _large_. (and its devs have no interest in being firmware agnostic) > One thing I've noticed is that, having dropped Linux as a primary > payload, we are recreating lots of code for things li

[coreboot] [PATCH]libpayload: stub USB functions, if not compiled in

Hi, some people had issues with libpayload without USB features, and payloads failing to build because some functions were missing. This patch adds stubs in case USB is not selected. It's mostly a temporary measure, until there's some proper mechanism to figure out how libpayload was configured,

[coreboot] [PATCH]libpayload: weak usbdisk_* symbols

Hi, attached patch makes it optional for payloads to implement usbdisk_* functions if they don't need them. Regards, Patrick libpayload-patch-20081005-2-weak-usbdisk-functions Description: Binary data -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreb

Re: [coreboot] small bug/typo in libpayload

Jordan Crouse schrieb: > I thought we fixed this? What happened to that patch? > I just committed it. I also thought it was, but obviously, it wasn't. (r3641) Regards, Patrick -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] test for mailserver

-- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] [PATCH]libpayload: more capable USB drivers

integrated in both libc-getchar() and curses, if CONFIG_USB_HID is enabled Signed-off-by: Patrick Georgi <[EMAIL PROTECTED]> Regards, Patrick == --- include/libpayload.h(/coreboot/libpayload) (revision 2215)

[coreboot] [PATCH]libpayload: rework console interfaces

simple, stupid. Comments, critique and ideas for improvements welcome. Signed-off-by: Patrick Georgi <[EMAIL PROTECTED]> === libc/console.c == --- libc/console.c (revision 2218) +++ libc/console.c (local) @@ -31,

Re: [coreboot] libpayload: rework console interfaces

Jordan Crouse schrieb: > How does poll differ from havechar? Should we add a poll method to > the console drivers that is just null on most systems? > The usb poll code handles all usb related issues (eg. attach/detach of devices, handling interrupt queues like with usb hid). It should end up i

Re: [coreboot] [patch 6/7] libpayload: Add a strtoul() function

ration Tested build, reviewed, but no functional test. With that in mind, Acked-by: Patrick Georgi <[EMAIL PROTECTED]> -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

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