A bit of background: I work for Silicom USA and we have several platforms
designed around Denverton-NS. Prior to coming to Silicom I was a BIOS
architect for Intel, being employed there for 19 years. I was one of the
original BIOS engineers for Denverton back when it was first released and ADI
Another thing I'd like to say (and it's probably pretty obvious once the
majority of the commits start coming through) is that a lot of work has been
done for this. In order to make the commit chunks more logical in their
grouping will require that the build will end up breaking because changes
former coworkers at Intel. They are
having a meeting on Tuesday to discuss the support moving forward, but in all
likelihood they will pass on the maintenance to me (they've already asked me if
I'd be willing in fact).
-Original Message-
From: Angel Pons
Sent: Saturday, J
Pons
Sent: Saturday, January 8, 2022 8:43 AM
To: Jeff Daly
Cc: Felix Singer ; coreboot@coreboot.org
Subject: Re: [coreboot] Re: Denverton-NS refactoring
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opening attachments.
Hi Jeff,
On Fri, Jan 7, 2022 at 5:13 AM Jeff
Am 12.01.22 um 15:49 schrieb Jeff Daly:
> Ok, so what I've figured out is that it seems gerrit doesn't like it
> when the code gets refactored. I have several commits that are
> showing merge conflicts but the files that have conflicts are because
> a lot of code cha
hanged
in the file in the base I'm working on and by rebasing against master before
pushing, I'd see the merge conflict. If my change got in before someone elses,
then they'd see the merge conflict when they went to push.
-Original Message-
From: Nico Huber
Sent:
g the remaining changes to the
mainboards and adding my own platforms should be the end of it.
-Original Message-
From: Nico Huber
Sent: Wednesday, January 12, 2022 12:28 PM
To: Jeff Daly ; Paul Menzel ;
coreboot@coreboot.org
Subject: Re: [coreboot] Re: Gerrit shows a Merge Co
A quick note, the feedback I got from Intel is that they will be moving away
from internal support for DNV coreboot. The current maintainers at Intel will
be assigning myself as a main maintainer with Vanessa as Intel's PAE support.
-Original Message-
From: Jeff Daly
Sent: Wedn
ly 'drop'. If that's how my comment was
taken, for that I sincerely apologize.
-Original Message-
From: Szafranski, MariuszX
Sent: Wednesday, January 19, 2022 4:49 AM
To: Peter Stuge ; coreboot@coreboot.org; Jeff Daly
Subject: RE: [coreboot] Re: Gerrit shows a Merge Confl
0xFD000 is bdf 0/1f/5, not 0/1f/0
Is your SPI controller at function 5?That’s where it usually is for Intel
SoCs.
From: Rao G
Sent: Friday, January 28, 2022 8:31 AM
To: coreboot
Subject: [coreboot] SPIBAR + 0x10 offset with MMIOREAD32 causing exception
Caution: This is an external email. P
And your ECAM base address for PCIE is at 0xC000 ?
From: Rao G
Sent: Friday, January 28, 2022 11:21 AM
To: Jeff Daly ; coreboot
Subject: Re: [coreboot] SPIBAR + 0x10 offset with MMIOREAD32 causing exception
Caution: This is an external email. Please take care when clicking links or
What platform are we talking about here, and are you sure this isn’t a bit of
hardware that hasn’t been disabled during boot somehow?
From: Rao G
Sent: Friday, January 28, 2022 11:55 AM
To: Jeff Daly
Cc: coreboot
Subject: Re: [coreboot] SPIBAR + 0x10 offset with MMIOREAD32 causing exception
If I may chime in here (I worked at Intel back when this issue was first
encountered when porting coreboot to Jacobsville)… The way I ended up making
it work was to introduce another object in devicetree (which I called a root
bridge) to model the concept of the PCI stack. In the picture belo
> -Original Message-
> From: Nico Huber
> Sent: Tuesday, March 22, 2022 7:21 AM
> To: coreb...@akumat.pl; coreboot@coreboot.org
> Subject: [coreboot] Re: Multi domain PCI resource allocation: How to deal
> with multiple root busses on one domain
>
> Caution: This is an external email. P
Maybe dumb question but have you booted an Intel RVP with chrome EC yet? Is
the EC handling the power sequencing for the board?
> -Original Message-
> From: Sameeruddin Shaik
> Sent: Friday, March 25, 2022 6:59 AM
> To: Coreboot
> Subject: [coreboot] Building the coreboot image for the
do you have a bootable media?
From: Putsala Amar via coreboot
Sent: Tuesday, April 5, 2022 6:19 AM
To: coreboot@coreboot.org
Subject: [coreboot] Coreboot : Change/modify Boot maintenance manager for auto
boot support.
Caution: This is an external email. Please take care when clicking links or
Did you ever get this resolved?
From: Somanna Ankaiah via coreboot
Sent: Thursday, June 30, 2022 10:19 PM
To: coreboot@coreboot.org
Cc: Krishna Kishor G ; Maheshwar Reddy B
Subject: [coreboot] DDR4 detection issue in the Memory Down approach on the
intel Denverton board
Caution: This is an ex
esday, August 16, 2022 6:03 AM
To: Jeff Daly ; coreboot@coreboot.org
Cc: Krishna Kishor G ; Maheshwar Reddy B
Subject: Re: DDR4 detection issue in the Memory Down approach on the intel
Denverton board
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opening attachments.
You're looking at a communications platform where the PCH is actually something
called Cave Creek or Coleto Creek (depending on the XX number). The DMI for
Sandy/Ivy is 'DMI2' but at DMI1 speed, 2.5GT/s.
This PCH is a combination of Ibex Peak (with some IP removed/modified) and the
addition of
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