[coreboot] Proper way to obtain GbE.bin for Denverton atom

Hello Everyone, I am currently working on a custom Denverton board similar to the Intel Harcuvar board. I am working to enable the Intel Lan controller, Did anyone generate the GbE.binary(firmware) for the Intel Lan controller of denverton atom or should i check with Intel for binary? We are using

[coreboot] Re: Proper way to obtain GbE.bin for Denverton atom

Thank you Felix for the details. Intel FIT Tool does not provide other options except enabling the GbE region and option to add the binary file for Lan controller 0 and 1 region. I wanted to enable the region to properly initialize the pcie region as well to get the correct details for the Intel

[coreboot] Custom Denverton Board: UART Initialization issue.

Hi Everyone, I am currently working on a custom Denverton board similar to the Intel Harcuvar board. CAR is working and the ROM stage is executing. There should be console output on UART0, but it does not appear to be initializing. There is a logic analyzer connected directly to the SOC UART p

[coreboot] 4.12 Tags Release VBOOT_HOST_BUILD Issue

Hello Everybody, Could anyone face the build issue in 4.12 while compiling the CBFS VBOOT_HOST_BUILD? Is there option available to disable VBOOT_HOST_BUILD ? or Does the host machine has to have any specifics libraries installed? Please throw any insights. -- Thanks, Balaji ___

[coreboot] Flashing coreboot and Intel Flash Descriptor Erase Issue

We are using SPI flash(Macronix) to program the BIOS. And we use an external programmer to flash the BIOS (coreboot including FD+ME) into SPI Flash (16384 kB, SPI), it works fine and boots well. The board is functional and we have successfully booted a kernel on it. Am working on adding a feature

[coreboot] Flashing coreboot and Intel Flash Descriptor Erase Issue

Hello Everyone, We are using SPI flash(Macronix) to program the BIOS. And we use an external programmer to flash the BIOS (coreboot including FD+ME) into SPI Flash (16384 kB, SPI), it works fine and boots well. The board is functional and we have successfully booted a kernel on it. Am working on

[coreboot] Re: Flashing coreboot and Intel Flash Descriptor Erase Issue

gt; 1. Platform/SoC ? > 2. Verbose flashrom output(append -VVV in commandline) > > Regards, > Naresh > > On Wed, Oct 14, 2020 at 8:03 PM Balaji Sivakumar > wrote: > >> Hello Everyone, >> >> We are using SPI flash(Macronix) to program the BIOS. And we use an >

[coreboot] Re: Flashing coreboot and Intel Flash Descriptor Erase Issue

ot;Denverton", enable_flash_pch100}, > & compile flashrom. > > Regards, > Naresh > > On Wed, Oct 14, 2020 at 9:03 PM Balaji Sivakumar > wrote: > >> Hi Naresh, >> >> Please find the details. >> >> 1.Platform/SOC ? -> Intel atom Den

[coreboot] Re: Flashing coreboot and Intel Flash Descriptor Erase Issue

logs of flashrom that SMM protection is enabled. Working on it to disable it. Thanks Balaji On Fri, Oct 16, 2020 at 8:11 AM Peter Stuge wrote: > Balaji Sivakumar wrote: > > Am working on adding a feature to upgrading the BIOS (complete > > IFD+ME+Coreboot) using intel-spi driver

[coreboot] Re: Flashing coreboot and Intel Flash Descriptor Erase Issue

logs BIOS region SMM protection is enabled and changing it to writable at Bios control failed(Warning: Setting Bios Control at 0xdc from 0xab to 0x89 failed).It remains with oldervalue. On Sun, Oct 18, 2020 at 2:42 PM David Hendricks wrote: > On Sun, Oct 18, 2020 at 8:52 AM Balaji Sivakumar > w

[coreboot] Re: Flashing coreboot and Intel Flash Descriptor Erase Issue

ds to unlock / disable the Bios Write enable(BIOS_CNTL) or to access the HSFS registers to set the FLOCKDN bit to 0. Any pointers would be appreciated! Thanks, Balaji On Wed, Oct 14, 2020 at 12:42 PM Balaji Sivakumar wrote: > Thanks Naresh for the details. I will add the support in the flas

[coreboot] Re: Flashing coreboot and Intel Flash Descriptor Erase Issue

nlock / disable the Bios Write enable(BIOS_CNTL) or to access the HSFS registers to set the FLOCKDN bit to 0. Any pointers would be appreciated! On Sun, Oct 18, 2020 at 4:20 PM Balaji Sivakumar wrote: > There is some documentation in the tree to help explain the "opaque flash >

[coreboot] Re: Flashing coreboot and Intel Flash Descriptor Erase Issue

Hi David, Have verified and confirmed that coreboot process as well, it is disabling the BIOS write protect and Enable Prefetching and Caching as part of fast_spi_init(). /* Disable the BIOS write protect so write commands are allowed. */ bios_cntl &= ~SPIBAR_BIOS_CONTROL_EISS; bios_c

[coreboot] Re: Flashing coreboot and Intel Flash Descriptor Erase Issue

> > > On Tue, Nov 10, 2020 at 12:40 PM David Hendricks < > david.hendri...@gmail.com> wrote: > >> Hi Balaji, >> >> On Tue, Nov 3, 2020 at 10:03 PM Balaji Sivakumar < >> shivbalaji1...@gmail.com> wrote: >> >>> >>>

[coreboot] Re: Flashing coreboot and Intel Flash Descriptor Erase Issue

6:42 PM Balaji Sivakumar wrote: > Naresh, > > I have added Denverton support in the flashrom and I found that SMM > Protection is enabled from the logs. > > I have tried to disable it using setcpi utility and it remains the same > value. Also the flashrom utility also tri