[coreboot] Jasper Lake: Commit 21e61847 (ramtop caching) causes FSP-M to fail with EFI_UNSUPPORTED

For Librem 11 (Intel N5100, Jasper Lake), I had to revert 21e61847 [1] in order for FspMemoryInit to succeed for second and later boots. If the MTRR is set in early_ramtop_enable_cache_range(), all JSL FSPs I tested fail FspMemoryInit with EFI_UNSUPPORTED.  Since the

[coreboot] Re: Jasper Lake: Commit 21e61847 (ramtop caching) causes FSP-M to fail with EFI_UNSUPPORTED

I already pushed a revert: https://review.coreboot.org/c/coreboot/+/78091 Intel stated they have no intention of releasing a public FSP for JSL unfortuantely On Fri, Sep 22, 2023 at 10:01 AM Jonathon Hall wrote: > For Librem 11 (Intel N5100, Jasper Lake), I had to revert 21e61847 [1] in > order

[coreboot] Re: RFC: Post-build control of serial console

Hi, Here is an updated version 2 of the RFC RFCv2: Post-build control of serial console It is annoying to have to create and maintain two completely different builds of coreboot just to enable or disable the console. It would be much more convenient to have a 'silent' flag in the image, which ca