Hi Sven,
On 11.06.21 00:55, Sven Semmler wrote:
> this is my first time posting here and it is quite possible that I've
> overlooked something obvious. In that case please just point me to
> whatever I should have read and accept my apologies.
don't worry. If this were documented, I would have mi
Hi Nico, Sven,
On Fri, Jun 11, 2021 at 9:19 AM Nico Huber wrote:
>
> Hi Sven,
>
> On 11.06.21 00:55, Sven Semmler wrote:
> > On my ThinkPad T430 running Coreboot-4.8.1 as part of an Heads install,
> > I see these error messages when turning on the PC:
> >
> > mce: [Hardware Error]: CPU 0: Machine
Dear Angel,
Am 11.06.21 um 12:05 schrieb Angel Pons:
On Fri, Jun 11, 2021 at 9:19 AM Nico Huber wrote:
On 11.06.21 00:55, Sven Semmler wrote:
On my ThinkPad T430 running Coreboot-4.8.1 as part of an Heads install,
I see these error messages when turning on the PC:
mce: [Hardware Error]:
Hi Angel,
Long time no speak. Hope you are well.
Sven is using 4.8.1 as its a Heads based installation.I see the patch went
in Sept 2018 which is a fair few months after 4.8.1. Ill port a heads build
with 4.11 for Sven (and myself, as I have the same issue) and see if that
resolves.
cheers
Simon
Hi Sumo,
It should be simple as adding SPI early init to bootblock.
You could try to add call to
fast_spi_early_init(DEFAULT_SPI_BASE);
at the end of bootblock_soc_early_init function from
src/soc/intel/denverton_ns/bootblock/bootblock.c
I suspect that after that MRC writing should also work in e
Hi,
Please find the latest report on new defect(s) introduced to coreboot found
with Coverity Scan.
1 new defect(s) introduced to coreboot found with Coverity Scan.
New defect(s) Reported-by: Coverity Scan
Showing 1 of 1 defect(s)
** CID 1457506: Null pointer dereferences (REVERSE_INULL)
/
what's the likely hood that i can get coreboot to run on a tyan gpu server?
this one specifically:
https://www.tyan.com/Barebones_FT77DB7109_B7109F77DV14HR-2T-NFZ
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On 6/11/21 4:18 AM, Nico Huber wrote:
0xfefe..0xfeff is a range used for cache- as-ram (CAR) which
is a mode where the processor cache is used as RAM before the actual
DRAM is available.
Thank you Nico for the insight!
On 6/11/21 5:05 AM, Angel Pons wrote:
They look a lot like what ht
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