[coreboot] coreboot not starting on denverton_ns

2021-06-10 Thread Sumo
Hi, Coreboot is not starting on denverton due to this commit: * 0f068a600e drivers/intel/fsp2_0: Fix the FSP-T position (found this by doing a manual git bisect using an old commit as reference, everything was working good around november 2020) Basically it crashes, nothing is shown in the console

[coreboot] Re: coreboot not starting on denverton_ns

2021-06-10 Thread Arthur Heymans
Hi Try with https://review.coreboot.org/c/coreboot/+/55389 applied. Kind regards Arthur On Thu, Jun 10, 2021 at 3:16 PM Sumo wrote: > Hi, > > Coreboot is not starting on denverton due to this commit: > * 0f068a600e drivers/intel/fsp2_0: Fix the FSP-T position > (found this by doing a manual gi

[coreboot] Re: coreboot not starting on denverton_ns

2021-06-10 Thread Sumo
Hi Arthur, It works, thanks! Kind regards, Sumo On Thu, Jun 10, 2021 at 10:36 AM Arthur Heymans wrote: > Hi > > Try with https://review.coreboot.org/c/coreboot/+/55389 applied. > > Kind regards > Arthur > > On Thu, Jun 10, 2021 at 3:16 PM Sumo wrote: > >> Hi, >> >> Coreboot is not starting on

[coreboot] denverton_ns: failed to write RW_MRC_CACHE

2021-06-10 Thread Sumo
Hi, I'm stuck in a problem where coreboot fails to write the MRC cache in the SPI Flash. Below is the log output: FMAP: area RW_MRC_CACHE found @ 81 (65536 bytes) MRC: Checking cached data update for 'RW_MRC_CACHE'. SF: Detected 00 with sector size 0x1000, total 0x100 MRC: no data in

[coreboot] Re: denverton_ns: failed to write RW_MRC_CACHE

2021-06-10 Thread Mariusz Szafrański via coreboot
Hi Sumo, Please try to additionally select MRC_WRITE_NV_LATE or BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES to push MRC writing to later state W dniu 10.06.2021 o 16:58, Sumo pisze: Hi, I'm stuck in a problem where coreboot fails to write the MRC cache in the SPI Flash. Below is the log output:

[coreboot] Re: denverton_ns: failed to write RW_MRC_CACHE

2021-06-10 Thread Sumo
Hi Mariusz, Setting BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES solved the problem, thanks! The only drawback of saving MRC CACHE in later state are the additional resets which are requested by FSP_S (silicon init) - for each additional reset the DDR4 training data is lost and this delays the startup a

[coreboot] coreboot-4.8.1 ... mce errors

2021-06-10 Thread Sven Semmler
Hi, this is my first time posting here and it is quite possible that I've overlooked something obvious. In that case please just point me to whatever I should have read and accept my apologies. On my ThinkPad T430 running Coreboot-4.8.1 as part of an Heads install, I see these error messages