Hi,
Coreboot is not starting on denverton due to this commit:
* 0f068a600e drivers/intel/fsp2_0: Fix the FSP-T position
(found this by doing a manual git bisect using an old commit as reference,
everything was working good around november 2020)
Basically it crashes, nothing is shown in the console
Hi
Try with https://review.coreboot.org/c/coreboot/+/55389 applied.
Kind regards
Arthur
On Thu, Jun 10, 2021 at 3:16 PM Sumo wrote:
> Hi,
>
> Coreboot is not starting on denverton due to this commit:
> * 0f068a600e drivers/intel/fsp2_0: Fix the FSP-T position
> (found this by doing a manual gi
Hi Arthur,
It works, thanks!
Kind regards,
Sumo
On Thu, Jun 10, 2021 at 10:36 AM Arthur Heymans wrote:
> Hi
>
> Try with https://review.coreboot.org/c/coreboot/+/55389 applied.
>
> Kind regards
> Arthur
>
> On Thu, Jun 10, 2021 at 3:16 PM Sumo wrote:
>
>> Hi,
>>
>> Coreboot is not starting on
Hi,
I'm stuck in a problem where coreboot fails to write the MRC cache in the
SPI Flash.
Below is the log output:
FMAP: area RW_MRC_CACHE found @ 81 (65536 bytes)
MRC: Checking cached data update for 'RW_MRC_CACHE'.
SF: Detected 00 with sector size 0x1000, total 0x100
MRC: no data in
Hi Sumo,
Please try to additionally select MRC_WRITE_NV_LATE or
BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES to push MRC writing to later state
W dniu 10.06.2021 o 16:58, Sumo pisze:
Hi,
I'm stuck in a problem where coreboot fails to write the MRC cache in
the SPI Flash.
Below is the log output:
Hi Mariusz,
Setting BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES solved the problem, thanks!
The only drawback of saving MRC CACHE in later state are the additional
resets which are requested by FSP_S (silicon init) - for each additional
reset the DDR4 training data is lost and this delays the startup a
Hi,
this is my first time posting here and it is quite possible that I've
overlooked something obvious. In that case please just point me to
whatever I should have read and accept my apologies.
On my ThinkPad T430 running Coreboot-4.8.1 as part of an Heads install,
I see these error messages
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