[coreboot] IO resources with base == 0/LPC decode

Dear coreboot folks, Arthur provided change-set *sb/amd/hudson: Skip setting up LPC decode for base < 0x20* [1] fixing a hang when doing `outb(0, DMA1_RESET_REG)` on the Asus F2A85-M PRO with Nuvoton NCT6779D: In some board ports SuperIO chips in the devicetree are not properly set up with

[coreboot] Re: link time optimization testing

>> I haven't had much luck in finding options for recovery. Ideally I'd >> like something like the dual switched bios in the old wiki but >> toggle-able electronically ie. gpio pin from spare router w/ Openwrt. > >That's the product BIOS Savior RD1 from Taiwanese IOSS, switched by a >jumper which c

[coreboot] DiskonChip 2000 testing (& old coreboot_v1/linux_bios)

Well, I'm finally getting around to writing this, though I'm still not all that comfortable bringing it up. I purchased a diskonchip 2000 266mb a while ago just to mess around with. It took a long time in shipping though and then it took me a while to actually try to test it out. I had thought I c