[coreboot] Re: Coffee Lake Reset S5 Problem

2023-03-29 Thread Maximilian Brune
Not really familiar with the PIC32, but do you have some kind of logs for it? The PIC32 should get the usual power sequence signals from the PCH and acknowledge them before the host gets back to the reset vector. I had a similar case in the past where the PCH repeated sending the power sequencing s

[coreboot] Re: Coffee Lake Reset S5 Problem

2023-03-28 Thread cagataybag--- via coreboot
Our design is similar to RVP except that we have PIC32 instead of EC and we have RAM soldered on board. So power sequences and other settings are controlled by PIC32. The only changes I did are putting appropriate spd binary and changing spd read type. I added log as attachment. I am building f

[coreboot] Re: Coffee Lake Reset S5 Problem

2023-03-28 Thread Maximilian Brune
What do you mean by "microcontroller"? ME? EC? Does it work on the reference BIOS? Which EC Firmware are you using? Am Di., 28. März 2023 um 16:00 Uhr schrieb Paul Menzel < pmen...@molgen.mpg.de>: > > Dear Cagatay, > > > Welcome to coreboot! > > Am 28.03.23 um 15:49 schrieb cagatay bagci via core

[coreboot] Re: Coffee Lake Reset S5 Problem

2023-03-28 Thread Paul Menzel
Dear Cagatay, Welcome to coreboot! Am 28.03.23 um 15:49 schrieb cagatay bagci via coreboot: We have a custom CFL board that resembles CFL RVP-11. I compiled the code and flashed it and it started booting without problem. However after global reset, it stucks at S5 and S5 signal asserts low. B