[clang] [RISCV] Handle empty structs/unions passing in C++ (PR #97315)

https://github.com/svs-quic created https://github.com/llvm/llvm-project/pull/97315 According to RISC-V integer calling convention empty structs or union arguments or return values are ignored by C compilers which support them as a non-standard extension. This is not the case for C++, which re

[clang] [RISCV] Handle empty structs/unions passing in C++ (PR #97315)

svs-quic wrote: Just waiting for the pre-checkins to complete. https://github.com/llvm/llvm-project/pull/97315 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Handle empty structs/unions passing in C++ (PR #97315)

https://github.com/svs-quic ready_for_review https://github.com/llvm/llvm-project/pull/97315 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Handle empty structs/unions passing in C++ (PR #97315)

svs-quic wrote: Thanks @efriedma-quic. I tried adding a test case for it locally and see that the code produced is different for llvm and gcc: https://godbolt.org/z/vdhGbvj6W Test case: ``` struct s12 {int x[0];}; struct s12 test_s12(struct s12 a) { return a; } ``` For llvm this is an empty r

[clang] [RISCV] Handle empty structs/unions passing in C++ (PR #97315)

https://github.com/svs-quic updated https://github.com/llvm/llvm-project/pull/97315 >From 3c744fe6111f0b6d24356a584f94c6d1cb273f7a Mon Sep 17 00:00:00 2001 From: Sudharsan Veeravalli Date: Mon, 1 Jul 2024 21:58:37 +0530 Subject: [PATCH 1/2] [RISCV] Handle empty structs/unions passing in C++ --

[clang] [RISCV] Handle empty structs/unions passing in C++ (PR #97315)

https://github.com/svs-quic updated https://github.com/llvm/llvm-project/pull/97315 >From 3c744fe6111f0b6d24356a584f94c6d1cb273f7a Mon Sep 17 00:00:00 2001 From: Sudharsan Veeravalli Date: Mon, 1 Jul 2024 21:58:37 +0530 Subject: [PATCH 1/3] [RISCV] Handle empty structs/unions passing in C++ --

[clang] [RISCV] Handle empty structs/unions passing in C++ (PR #97315)

svs-quic wrote: > The current spec language is: > > > Empty structs or union arguments or return values are ignored by C > > compilers which support them as a non-standard extension. This is not the > > case for C++, which requires them to be sized types. > > So empty structs in C are ignored

[clang] [RISCV] Handle empty structs/unions passing in C++ (PR #97315)

svs-quic wrote: > Thanks @efriedma-quic. I tried adding a test case for it locally and see that > the code produced is different for llvm and gcc: > https://godbolt.org/z/vdhGbvj6W > > Test case: > > ``` > struct s12 {int x[0];}; > struct s12 test_s12(struct s12 a) { > return a; > } > ``` >

[clang] [RISCV] Handle empty structs/unions passing in C++ (PR #97315)

https://github.com/svs-quic updated https://github.com/llvm/llvm-project/pull/97315 >From 3c744fe6111f0b6d24356a584f94c6d1cb273f7a Mon Sep 17 00:00:00 2001 From: Sudharsan Veeravalli Date: Mon, 1 Jul 2024 21:58:37 +0530 Subject: [PATCH 1/4] [RISCV] Handle empty structs/unions passing in C++ --

[clang] [RISCV] Handle empty structs/unions passing in C++ (PR #97315)

svs-quic wrote: Thanks. I have modified the check and added a relevant test for empty arrays. https://github.com/llvm/llvm-project/pull/97315 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-co

[clang] [RISCV] Handle empty structs/unions passing in C++ (PR #97315)

svs-quic wrote: Could someone please merge this change? I do not have permissions to do so. https://github.com/llvm/llvm-project/pull/97315 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-comm

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcia (Arithmetic) extension (PR #118076)

https://github.com/svs-quic created https://github.com/llvm/llvm-project/pull/118076 This extension adds 11 instructions that perform integer arithmetic. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/latest This patch adds assembler only support. >From 42

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcia (Arithmetic) extension (PR #118076)

https://github.com/svs-quic updated https://github.com/llvm/llvm-project/pull/118076 >From f1031947890501ba543ee9c937110f75379f2069 Mon Sep 17 00:00:00 2001 From: Sudharsan Veeravalli Date: Fri, 29 Nov 2024 14:25:31 +0530 Subject: [PATCH] [RISCV] Add Qualcomm uC Xqcia (Arithmetic) extension Th

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcia (Arithmetic) extension (PR #118076)

https://github.com/svs-quic closed https://github.com/llvm/llvm-project/pull/118076 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcia (Arithmetic) extension (PR #118076)

svs-quic wrote: Don't think force push was the right thing to do here. I'll put up another PR. Closing this. https://github.com/llvm/llvm-project/pull/118076 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailma

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcia (Arithmetic) extension (PR #118113)

https://github.com/svs-quic created https://github.com/llvm/llvm-project/pull/118113 This extension adds 11 instructions that perform integer arithmetic. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/latest This patch adds assembler only support. >From 32

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcisls (Scaled Load Store) extension (PR #117987)

https://github.com/svs-quic closed https://github.com/llvm/llvm-project/pull/117987 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcisls (Scaled Load Store) extension (PR #117987)

https://github.com/svs-quic created https://github.com/llvm/llvm-project/pull/117987 This extension adds 8 load/store instructions with a scaled index addressing mode. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/latest This patch adds assembler only sup

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcicsr (CSR) extension (PR #117169)

https://github.com/svs-quic updated https://github.com/llvm/llvm-project/pull/117169 >From 92a3e2e9c44c03093e6050b92b938fd2a0d6886c Mon Sep 17 00:00:00 2001 From: Sudharsan Veeravalli Date: Wed, 20 Nov 2024 13:24:07 +0530 Subject: [PATCH 1/4] [RISCV] Add Qualcomm uC Xqcicsr (CSR) extension The

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcicsr (CSR) extension (PR #117169)

@@ -771,6 +771,10 @@ Error RISCVISAInfo::checkDependency() { return getIncompatibleError("xwchc", "zcb"); } + if (Exts.count("xqcicsr") != 0 && (XLen != 32)) { +return getError("'xqcicsr' is only supported in 'rv32'"); svs-quic wrote: Done https

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcicsr (CSR) extension (PR #117169)

@@ -0,0 +1,19 @@ +# Xqcicsr - Qualcomm uC CSR Extension +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcicsr -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experim

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcicsr (CSR) extension (PR #117169)

https://github.com/svs-quic updated https://github.com/llvm/llvm-project/pull/117169 >From 92a3e2e9c44c03093e6050b92b938fd2a0d6886c Mon Sep 17 00:00:00 2001 From: Sudharsan Veeravalli Date: Wed, 20 Nov 2024 13:24:07 +0530 Subject: [PATCH 1/3] [RISCV] Add Qualcomm uC Xqcicsr (CSR) extension The

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcicsr (CSR) extension (PR #117169)

https://github.com/svs-quic updated https://github.com/llvm/llvm-project/pull/117169 >From 92a3e2e9c44c03093e6050b92b938fd2a0d6886c Mon Sep 17 00:00:00 2001 From: Sudharsan Veeravalli Date: Wed, 20 Nov 2024 13:24:07 +0530 Subject: [PATCH 1/5] [RISCV] Add Qualcomm uC Xqcicsr (CSR) extension The

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcicsr (CSR) extension (PR #117169)

@@ -0,0 +1,44 @@ +//=== RISCVInstrInfoXQci.td *- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apa

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcicsr (CSR) extension (PR #117169)

https://github.com/svs-quic closed https://github.com/llvm/llvm-project/pull/117169 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcisls (Scaled Load Store) extension (PR #117987)

https://github.com/svs-quic updated https://github.com/llvm/llvm-project/pull/117987 >From 3d7772894ae10d79570899dbdfb34fd4877a37e5 Mon Sep 17 00:00:00 2001 From: Sudharsan Veeravalli Date: Thu, 28 Nov 2024 15:11:57 +0530 Subject: [PATCH 1/3] [RISCV] Add Qualcomm uC Xqcisls (Scaled Load Store)

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcisls (Scaled Load Store) extension (PR #117987)

@@ -771,9 +772,11 @@ Error RISCVISAInfo::checkDependency() { return getIncompatibleError("xwchc", "zcb"); } - if (Exts.count("xqcicsr") != 0 && (XLen != 32)) { -return getError("'xqcicsr' is only supported for 'rv32'"); - } + for (auto Ext : XqciExts) +if (E

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcisls (Scaled Load Store) extension (PR #117987)

https://github.com/svs-quic updated https://github.com/llvm/llvm-project/pull/117987 >From 3d7772894ae10d79570899dbdfb34fd4877a37e5 Mon Sep 17 00:00:00 2001 From: Sudharsan Veeravalli Date: Thu, 28 Nov 2024 15:11:57 +0530 Subject: [PATCH 1/2] [RISCV] Add Qualcomm uC Xqcisls (Scaled Load Store)

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcisls (Scaled Load Store) extension (PR #117987)

@@ -22,6 +22,28 @@ // Instruction Class Templates //===--===// +let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in { +class QCILoad_ScaleIdx func4, string opcodestr> +: RVInstRBase<0b111, OPC_CUSTOM_0,

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcisls (Scaled Load Store) extension (PR #117987)

@@ -771,9 +772,11 @@ Error RISCVISAInfo::checkDependency() { return getIncompatibleError("xwchc", "zcb"); } - if (Exts.count("xqcicsr") != 0 && (XLen != 32)) { -return getError("'xqcicsr' is only supported for 'rv32'"); - } + for (auto Ext : XqciExts) +if (E

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcicsr (CSR) extension (PR #117169)

https://github.com/svs-quic updated https://github.com/llvm/llvm-project/pull/117169 >From 92a3e2e9c44c03093e6050b92b938fd2a0d6886c Mon Sep 17 00:00:00 2001 From: Sudharsan Veeravalli Date: Wed, 20 Nov 2024 13:24:07 +0530 Subject: [PATCH 1/2] [RISCV] Add Qualcomm uC Xqcicsr (CSR) extension The

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcia (Arithmetic) extension (PR #118113)

https://github.com/svs-quic closed https://github.com/llvm/llvm-project/pull/118113 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcicm (Conditional Move) extension (PR #121752)

https://github.com/svs-quic closed https://github.com/llvm/llvm-project/pull/121752 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcicli (Conditional Load Immediate) extension (PR #121292)

https://github.com/svs-quic closed https://github.com/llvm/llvm-project/pull/121292 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Qualcomm uC Xqciac (Load-Store Adress calculation) extension (PR #121037)

https://github.com/svs-quic closed https://github.com/llvm/llvm-project/pull/121037 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcicli (Conditional Load Immediate) extension (PR #121292)

https://github.com/svs-quic created https://github.com/llvm/llvm-project/pull/121292 This extension adds 12 instructions that conditionally load an immediate value. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/latest This patch adds assembler only support

[clang] [llvm] [RISCV] Add Qualcomm uC Xqciac (Load-Store Adress calculation) extension (PR #121037)

https://github.com/svs-quic updated https://github.com/llvm/llvm-project/pull/121037 >From 304147a932684d7ccc1a8343655bb64a0c7e238f Mon Sep 17 00:00:00 2001 From: Harsh Chandel Date: Tue, 24 Dec 2024 13:00:04 +0530 Subject: [PATCH 1/2] [RISCV] Add Qualcomm uC Xqciac (Load-Store Adress calculat

[clang] [llvm] [RISCV] Add Qualcomm uC Xqciac (Load-Store Adress calculation) extension (PR #121037)

@@ -184,6 +191,37 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { } // hasSideEffects = 0, mayLoad = 0, mayStore = 0 } // Predicates = [HasVendorXqcia, IsRV32], DecoderNamespace = "Xqcia" +let Predicates = [HasVendorXqciac, IsRV32], DecoderNamespace = "Xqciac" in { +

[clang] [llvm] [RISCV] Add Qualcomm uC Xqciac (Load-Store Adress calculation) extension (PR #121037)

@@ -184,6 +191,37 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { } // hasSideEffects = 0, mayLoad = 0, mayStore = 0 } // Predicates = [HasVendorXqcia, IsRV32], DecoderNamespace = "Xqcia" +let Predicates = [HasVendorXqciac, IsRV32], DecoderNamespace = "Xqciac" in { +

[clang] [llvm] [RISCV] Add Qualcomm uC Xqciac (Load-Store Adress calculation) extension (PR #121037)

@@ -184,6 +191,37 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { } // hasSideEffects = 0, mayLoad = 0, mayStore = 0 } // Predicates = [HasVendorXqcia, IsRV32], DecoderNamespace = "Xqcia" +let Predicates = [HasVendorXqciac, IsRV32], DecoderNamespace = "Xqciac" in { +

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcicli (Conditional Load Immediate) extension (PR #121292)

https://github.com/svs-quic updated https://github.com/llvm/llvm-project/pull/121292 >From 44b470c5798d5e160b1d3159a936b5e1737482b3 Mon Sep 17 00:00:00 2001 From: Sudharsan Veeravalli Date: Sun, 29 Dec 2024 18:28:52 +0530 Subject: [PATCH 1/2] [RISCV] Add Qualcomm uC Xqcicli (Conditional Load I

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcics(Conditional Select) extension (PR #119504)

https://github.com/svs-quic closed https://github.com/llvm/llvm-project/pull/119504 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcics(Conditional Select) extension (PR #119504)

https://github.com/svs-quic approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/119504 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcilsm (Load Store Multiple) extension (PR #119823)

https://github.com/svs-quic created https://github.com/llvm/llvm-project/pull/119823 This extension adds 6 instructions that can do multi-word load/store. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/latest This patch adds assembler only support. >From 8

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcilsm (Load Store Multiple) extension (PR #119823)

https://github.com/svs-quic updated https://github.com/llvm/llvm-project/pull/119823 >From 87da7f670dcd0843c27bc533f62c710053ca4c86 Mon Sep 17 00:00:00 2001 From: Sudharsan Veeravalli Date: Fri, 13 Dec 2024 12:06:33 +0530 Subject: [PATCH 1/2] [RISCV] Add Qualcomm uC Xqcilsm (Load Store Multiple

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcilsm (Load Store Multiple) extension (PR #119823)

https://github.com/svs-quic closed https://github.com/llvm/llvm-project/pull/119823 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcicsr (CSR) extension (PR #117169)

https://github.com/svs-quic created https://github.com/llvm/llvm-project/pull/117169 The Qualcomm uC Xqcicsr extension adds 2 instructions that can read and write CSRs. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/latest This patch adds assembler only su

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcicsr (CSR) extension (PR #117169)

https://github.com/svs-quic updated https://github.com/llvm/llvm-project/pull/117169 >From 92a3e2e9c44c03093e6050b92b938fd2a0d6886c Mon Sep 17 00:00:00 2001 From: Sudharsan Veeravalli Date: Wed, 20 Nov 2024 13:24:07 +0530 Subject: [PATCH 1/2] [RISCV] Add Qualcomm uC Xqcicsr (CSR) extension The

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcicsr (CSR) extension (PR #117169)

@@ -329,6 +329,9 @@ The primary goal of experimental support is to assist in the process of ratifica ``experimental-smctr``, ``experimental-ssctr`` LLVM implements the `1.0-rc3 specification `__.

[clang] [llvm] [RISCV] Add Qualcomm uC Xqciint (Interrupts) extension (PR #122256)

@@ -742,8 +742,8 @@ Error RISCVISAInfo::checkDependency() { bool HasZvl = MinVLen != 0; bool HasZcmt = Exts.count("zcmt") != 0; static constexpr StringLiteral XqciExts[] = { - {"xqcia"}, {"xqciac"}, {"xqcicli"}, {"xqcicm"}, - {"xqcics"}, {"xqcicsr"}, {"xqcilsm

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcilo (Large Offset Load Store) extension (PR #123881)

https://github.com/svs-quic closed https://github.com/llvm/llvm-project/pull/123881 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Qualcomm uC Xqciint (Interrupts) extension (PR #122256)

https://github.com/svs-quic closed https://github.com/llvm/llvm-project/pull/122256 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcilia (Large Immediate Arithmetic) extension (PR #124706)

https://github.com/svs-quic approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/124706 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcisim (Simulation Hint) extension (PR #128833)

https://github.com/svs-quic updated https://github.com/llvm/llvm-project/pull/128833 >From 10f62d3697b3e2d773d828fc3e7a6767ff71a072 Mon Sep 17 00:00:00 2001 From: Sudharsan Veeravalli Date: Wed, 26 Feb 2025 12:13:32 +0530 Subject: [PATCH 1/2] [RISCV] Add Qualcomm uC Xqcisim (Simulation Hint] e

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcisim (Simulation Hint) extension (PR #128833)

@@ -485,6 +498,43 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { } // hasSideEffects = 0, mayLoad = 0, mayStore = 0 } // Predicates = [HasVendorXqcilia, IsRV32] +let Predicates = [HasVendorXqcisim, IsRV32] in { +let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in {

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcisim (Simulation Hint) extension (PR #128833)

@@ -485,6 +498,43 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { } // hasSideEffects = 0, mayLoad = 0, mayStore = 0 } // Predicates = [HasVendorXqcilia, IsRV32] +let Predicates = [HasVendorXqcisim, IsRV32] in { +let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in {

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcisim (Simulation Hint) extension (PR #128833)

@@ -485,6 +498,43 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { } // hasSideEffects = 0, mayLoad = 0, mayStore = 0 } // Predicates = [HasVendorXqcilia, IsRV32] +let Predicates = [HasVendorXqcisim, IsRV32] in { +let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in {

[clang] [llvm] [RISCV] Xqcia 0.4 Spec renamed qc.(sla/sll)sat to qc.(shl/shlu)sat (PR #128710)

https://github.com/svs-quic approved this pull request. LGTM. Please remove "[RISCV] Xqcia 0.4 Spec renamed qc.(sla/sll)sat to qc.(shl/shlu)sat" from the commit message body before merging. https://github.com/llvm/llvm-project/pull/128710 ___ cfe-comm

[clang] [llvm] [RISCV] Assembler support for XRivosVizip (PR #127694)

svs-quic wrote: Could you please add an entry in the release notes for this? https://github.com/llvm/llvm-project/pull/127694 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcisim (Simulation Hint) extension (PR #128833)

https://github.com/svs-quic created https://github.com/llvm/llvm-project/pull/128833 This extension adds 10 instructions that provide hints to the interface simulation environment. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/ This patch adds assembler o

[clang] [llvm] [RISCV] Add Xqccmp Assembly Support (PR #128731)

@@ -0,0 +1,95 @@ +//=== RISCVInstrInfoXqccmp.td --*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apa

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcisim (Simulation Hint) extension (PR #128833)

https://github.com/svs-quic updated https://github.com/llvm/llvm-project/pull/128833 >From 10f62d3697b3e2d773d828fc3e7a6767ff71a072 Mon Sep 17 00:00:00 2001 From: Sudharsan Veeravalli Date: Wed, 26 Feb 2025 12:13:32 +0530 Subject: [PATCH 1/2] [RISCV] Add Qualcomm uC Xqcisim (Simulation Hint] e

[clang] [llvm] [RISCV] Add Qualcomn uC Xqcili (load large immediates) extension (PR #130012)

@@ -588,6 +590,19 @@ let Predicates = [HasVendorXqcilo, IsRV32] in { def QC_E_SW: QCIRVInstESStore<0b110, 0b11, "qc.e.sw">; } // Predicates = [HasVendorXqcilo, IsRV32] +let Predicates = [HasVendorXqcili, IsRV32] in { +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in

[clang] [llvm] [RISCV] Add Qualcomn uC Xqcili (load large immediates) extension (PR #130012)

@@ -1358,6 +1358,12 @@ def HasVendorXqciint AssemblerPredicate<(all_of FeatureVendorXqciint), "'Xqciint' (Qualcomm uC Interrupts Extension)">; +def FeatureVendorXqcili : RISCVExperimentalExtension<0, 2, "Qualcomm uC Load Large Immediate Extensio

[clang] [llvm] [RISCV] Add Qualcomn uC Xqcili (load large immediates) extension (PR #130012)

https://github.com/svs-quic commented: Please add entries in RISCVUsage.rst and ReleaseNotes.md. https://github.com/llvm/llvm-project/pull/130012 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cf

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcisim (Simulation Hint) extension (PR #128833)

https://github.com/svs-quic updated https://github.com/llvm/llvm-project/pull/128833 >From 10f62d3697b3e2d773d828fc3e7a6767ff71a072 Mon Sep 17 00:00:00 2001 From: Sudharsan Veeravalli Date: Wed, 26 Feb 2025 12:13:32 +0530 Subject: [PATCH 1/2] [RISCV] Add Qualcomm uC Xqcisim (Simulation Hint] e

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcisim (Simulation Hint) extension (PR #128833)

https://github.com/svs-quic updated https://github.com/llvm/llvm-project/pull/128833 >From 10f62d3697b3e2d773d828fc3e7a6767ff71a072 Mon Sep 17 00:00:00 2001 From: Sudharsan Veeravalli Date: Wed, 26 Feb 2025 12:13:32 +0530 Subject: [PATCH 1/3] [RISCV] Add Qualcomm uC Xqcisim (Simulation Hint] e

[clang] [llvm] [RISCV] Add Qualcomn uC Xqcili (load large immediates) extension (PR #130012)

@@ -0,0 +1,21 @@ +# Xqcili - Qualcomm uC Load Large Immediate Extension +# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-xqcili < %s 2>&1 \ svs-quic wrote: Please add a run line with mattr=-experimental-xqcili https://github.com/llvm/llvm-project/pull/13

[clang] [llvm] [RISCV] Add Qualcomn uC Xqcili (load large immediates) extension (PR #130012)

svs-quic wrote: It looks like there are some conflicts. Please fix them before merging. Also just noticed that you have been updating the same commit with the changes requested in the reviews. Please have them as separate commits in the future so that we can know what changed. https://github.

[clang] [llvm] [RISCV] Add Qualcomn uC Xqcili (load large immediates) extension (PR #130012)

@@ -0,0 +1,27 @@ +# Xqcili - Qualcomm uC Load Large Immediate Extension +# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-xqcili < %s 2>&1 \ +# RUN: | FileCheck -check-prefixes=CHECK,CHECK-PLUS %s +# RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqcili < %s 2>&1

[clang] [llvm] [RISCV] Add Qualcomn uC Xqcili (load large immediates) extension (PR #130012)

https://github.com/svs-quic approved this pull request. LGTM! @lenary do you have any comments? https://github.com/llvm/llvm-project/pull/130012 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe

[clang] [llvm] [RISCV] Add Qualcomn uC Xqcili (load large immediates) extension (PR #130012)

https://github.com/svs-quic approved this pull request. LGTM! https://github.com/llvm/llvm-project/pull/130012 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Qualcomn uC Xqcili (load large immediates) extension (PR #130012)

@@ -588,6 +590,19 @@ let Predicates = [HasVendorXqcilo, IsRV32] in { def QC_E_SW: QCIRVInstESStore<0b110, 0b11, "qc.e.sw">; } // Predicates = [HasVendorXqcilo, IsRV32] +let Predicates = [HasVendorXqcili, IsRV32] in { +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in