Author: Shengchen Kan
Date: 2020-05-28T13:17:14+08:00
New Revision: 49544499954912c5a0f02014de53e0bc0234c7af
URL:
https://github.com/llvm/llvm-project/commit/49544499954912c5a0f02014de53e0bc0234c7af
DIFF:
https://github.com/llvm/llvm-project/commit/49544499954912c5a0f02014de53e0bc0234c7af.diff
Author: Shengchen Kan
Date: 2020-06-03T14:59:14+08:00
New Revision: ac47588bc4ff5927a01ed6fcd269ce86aba52a7c
URL:
https://github.com/llvm/llvm-project/commit/ac47588bc4ff5927a01ed6fcd269ce86aba52a7c
DIFF:
https://github.com/llvm/llvm-project/commit/ac47588bc4ff5927a01ed6fcd269ce86aba52a7c.diff
Author: Shengchen Kan
Date: 2020-04-09T19:34:12+08:00
New Revision: 792b10978dfdd424721fbf0ffd99c35d628f2321
URL:
https://github.com/llvm/llvm-project/commit/792b10978dfdd424721fbf0ffd99c35d628f2321
DIFF:
https://github.com/llvm/llvm-project/commit/792b10978dfdd424721fbf0ffd99c35d628f2321.diff
Author: Shengchen Kan
Date: 2020-06-08T23:14:16+08:00
New Revision: 2c63ea6eded3eed4018306363c28b7f63d7b5898
URL:
https://github.com/llvm/llvm-project/commit/2c63ea6eded3eed4018306363c28b7f63d7b5898
DIFF:
https://github.com/llvm/llvm-project/commit/2c63ea6eded3eed4018306363c28b7f63d7b5898.diff
Author: Shengchen Kan
Date: 2020-05-13T14:48:46+08:00
New Revision: ad60ff70eb56a7d198e613152f9974d5d4baabd4
URL:
https://github.com/llvm/llvm-project/commit/ad60ff70eb56a7d198e613152f9974d5d4baabd4
DIFF:
https://github.com/llvm/llvm-project/commit/ad60ff70eb56a7d198e613152f9974d5d4baabd4.diff
@@ -119,9 +119,13 @@ bool X86TargetInfo::initFeatureMap(
setFeatureEnabled(Features, F, true);
std::vector UpdatedFeaturesVec;
- bool HasEVEX512 = true;
+ std::vector UpdatedAVX10FeaturesVec;
+ int HasEVEX512 = -1;
KanRobert wrote:
Use std::optional
@@ -15,8 +15,12 @@
#define __AVX2INTRIN_H
/* Define the default attributes for the functions in this file. */
-#define __DEFAULT_FN_ATTRS256 __attribute__((__always_inline__, __nodebug__,
__target__("avx2"), __min_vector_width__(256)))
-#define __DEFAULT_FN_ATTRS128 __attribu
@@ -50,11 +50,11 @@ typedef __bf16 __m128bh __attribute__((__vector_size__(16),
__aligned__(16)));
/* Define the default attributes for the functions in this file. */
#define __DEFAULT_FN_ATTRS
\
- __attribute__((__always_
@@ -131,35 +135,50 @@ bool X86TargetInfo::initFeatureMap(
continue;
}
-if (Feature.substr(0, 7) == "+avx10.") {
- HasAVX10 = true;
- HasAVX512F = true;
- if (Feature.substr(Feature.size() - 3, 3) == "512") {
-HasEVEX512 = true;
- } els
@@ -131,35 +135,50 @@ bool X86TargetInfo::initFeatureMap(
continue;
}
-if (Feature.substr(0, 7) == "+avx10.") {
- HasAVX10 = true;
- HasAVX512F = true;
- if (Feature.substr(Feature.size() - 3, 3) == "512") {
-HasEVEX512 = true;
- } els
@@ -131,35 +135,50 @@ bool X86TargetInfo::initFeatureMap(
continue;
}
-if (Feature.substr(0, 7) == "+avx10.") {
- HasAVX10 = true;
- HasAVX512F = true;
- if (Feature.substr(Feature.size() - 3, 3) == "512") {
-HasEVEX512 = true;
- } els
@@ -131,35 +135,50 @@ bool X86TargetInfo::initFeatureMap(
continue;
}
-if (Feature.substr(0, 7) == "+avx10.") {
- HasAVX10 = true;
- HasAVX512F = true;
- if (Feature.substr(Feature.size() - 3, 3) == "512") {
-HasEVEX512 = true;
- } els
https://github.com/KanRobert approved this pull request.
LGTM. Maybe we can add some explanations about why we add attribute
`no-evex512` for intrinsics in the description of the PR. It's a little tricky.
https://github.com/llvm/llvm-project/pull/71318
__
https://github.com/KanRobert approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/72126
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KanRobert wrote:
Investigating, I almost forgot the mechanism of MS inline asm support...
https://github.com/llvm/llvm-project/pull/73207
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https://github.com/KanRobert approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/71317
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https://github.com/KanRobert approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/75571
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KanRobert wrote:
One more justification...
https://www.felixcloutier.com/x86/vscatterpf0dps:vscatterpf0qps:vscatterpf0dpd:vscatterpf0qpd
The assembler support for some KNL instructions is buggy
https://github.com/llvm/llvm-project/blob/31429e7a89590f88034920edd3e997aeabff8124/llvm/test/MC/X86/a
@@ -0,0 +1,34 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+;RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
--check-prefixes=X64
KanRobert wrote:
space between ; and RUN.
https://github.c
@@ -0,0 +1,34 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+;RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
--check-prefixes=X64
KanRobert wrote:
Could we use the default check prefix? `X6
@@ -0,0 +1,34 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+;RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
--check-prefixes=X64
+
+define i64 @sub8(i64 noundef %res, ptr %byte) {
+; X64-LABEL: sub8:
+; X64
@@ -1515,6 +1515,15 @@ def : Pat<(X86add_flag_nocf GR32:$src1, 128),
def : Pat<(X86add_flag_nocf GR64:$src1, 128),
(SUB64ri32 GR64:$src1, -128)>;
+// Depositing value to 8/16 bit subreg:
+def : Pat<(or (and GR64:$dst, -256),
+ (i64 (zextloadi8 addr:$src
https://github.com/KanRobert approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/75978
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https://github.com/KanRobert approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/73207
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https://github.com/KanRobert updated
https://github.com/llvm/llvm-project/pull/73672
>From 96464a9c37a532216e4df6c003aa1a8fcb448637 Mon Sep 17 00:00:00 2001
From: Samuel Tebbs
Date: Tue, 28 Nov 2023 16:22:32 +
Subject: [PATCH 1/2] [AArch64] Warn when calling a NEON builtin in a streaming
f
https://github.com/KanRobert created
https://github.com/llvm/llvm-project/pull/74199
Positive options: -mapx-features=
Negative options: -mno-apx-features=
-m[no-]apx-features is designed to be able to control separate APX
features.
Besides, we also support the flag -m[no-]apxf, which can be u
https://github.com/KanRobert updated
https://github.com/llvm/llvm-project/pull/74199
>From 246d6e2bc3f6fb60623b5d4c3f07b53c628ed88a Mon Sep 17 00:00:00 2001
From: Shengchen Kan
Date: Sat, 2 Dec 2023 23:52:53 +0800
Subject: [PATCH 1/2] [X86] Support CFE flags for APX features
Positive options:
https://github.com/KanRobert updated
https://github.com/llvm/llvm-project/pull/74199
>From 246d6e2bc3f6fb60623b5d4c3f07b53c628ed88a Mon Sep 17 00:00:00 2001
From: Shengchen Kan
Date: Sat, 2 Dec 2023 23:52:53 +0800
Subject: [PATCH 1/3] [X86] Support CFE flags for APX features
Positive options:
https://github.com/KanRobert edited
https://github.com/llvm/llvm-project/pull/74199
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@@ -5999,6 +5999,12 @@ def mno_gather : Flag<["-"], "mno-gather">,
Group,
HelpText<"Disable generation of gather instructions in
auto-vectorization(x86 only)">;
def mno_scatter : Flag<["-"], "mno-scatter">, Group,
HelpText<"Disable generatio
https://github.com/KanRobert updated
https://github.com/llvm/llvm-project/pull/74199
>From 246d6e2bc3f6fb60623b5d4c3f07b53c628ed88a Mon Sep 17 00:00:00 2001
From: Shengchen Kan
Date: Sat, 2 Dec 2023 23:52:53 +0800
Subject: [PATCH 1/4] [X86] Support CFE flags for APX features
Positive options:
@@ -927,6 +939,16 @@ void X86TargetInfo::getTargetDefines(const LangOptions
&Opts,
Builder.defineMacro("__USERMSR__");
if (HasCRC32)
Builder.defineMacro("__CRC32__");
+ if (HasEGPR)
+Builder.defineMacro("__EGPR__");
+ if (HasPush2Pop2)
+Builder.defineMacro(
https://github.com/KanRobert updated
https://github.com/llvm/llvm-project/pull/74199
>From 246d6e2bc3f6fb60623b5d4c3f07b53c628ed88a Mon Sep 17 00:00:00 2001
From: Shengchen Kan
Date: Sat, 2 Dec 2023 23:52:53 +0800
Subject: [PATCH 1/5] [X86] Support CFE flags for APX features
Positive options:
https://github.com/KanRobert updated
https://github.com/llvm/llvm-project/pull/74199
>From 246d6e2bc3f6fb60623b5d4c3f07b53c628ed88a Mon Sep 17 00:00:00 2001
From: Shengchen Kan
Date: Sat, 2 Dec 2023 23:52:53 +0800
Subject: [PATCH 1/6] [X86] Support CFE flags for APX features
Positive options:
@@ -422,3 +422,28 @@
// RUN: touch %t.o
// RUN: %clang -fdriver-only -Werror --target=x86_64-pc-linux-gnu
-mharden-sls=all %t.o -o /dev/null 2>&1 | count 0
+// RUN: %clang -target x86_64-unknown-linux-gnu -mapxf %s -### -o %t.o 2>&1 |
FileCheck -check-prefix=APXF %s
+// RUN:
https://github.com/KanRobert edited
https://github.com/llvm/llvm-project/pull/74199
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https://github.com/KanRobert updated
https://github.com/llvm/llvm-project/pull/74199
>From 246d6e2bc3f6fb60623b5d4c3f07b53c628ed88a Mon Sep 17 00:00:00 2001
From: Shengchen Kan
Date: Sat, 2 Dec 2023 23:52:53 +0800
Subject: [PATCH 1/7] [X86] Support CFE flags for APX features
Positive options:
@@ -5999,6 +5999,12 @@ def mno_gather : Flag<["-"], "mno-gather">,
Group,
HelpText<"Disable generation of gather instructions in
auto-vectorization(x86 only)">;
def mno_scatter : Flag<["-"], "mno-scatter">, Group,
HelpText<"Disable generatio
https://github.com/KanRobert updated
https://github.com/llvm/llvm-project/pull/74199
>From 246d6e2bc3f6fb60623b5d4c3f07b53c628ed88a Mon Sep 17 00:00:00 2001
From: Shengchen Kan
Date: Sat, 2 Dec 2023 23:52:53 +0800
Subject: [PATCH 1/8] [X86] Support CFE flags for APX features
Positive options:
@@ -422,3 +422,28 @@
// RUN: touch %t.o
// RUN: %clang -fdriver-only -Werror --target=x86_64-pc-linux-gnu
-mharden-sls=all %t.o -o /dev/null 2>&1 | count 0
+// RUN: %clang -target x86_64-unknown-linux-gnu -mapxf %s -### -o %t.o 2>&1 |
FileCheck -check-prefix=APXF %s
https://github.com/KanRobert edited
https://github.com/llvm/llvm-project/pull/74199
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KanRobert wrote:
@phoebewang Thanks for the review!
https://github.com/llvm/llvm-project/pull/74199
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https://github.com/KanRobert closed
https://github.com/llvm/llvm-project/pull/74199
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https://github.com/KanRobert approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/76389
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https://github.com/KanRobert approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/76420
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@@ -1056,6 +1056,22 @@ def CC_Intel_OCL_BI : CallingConv<[
CCDelegateTo
]>;
+def CC_X86_64_Preserve_None : CallingConv<[
+ // We don't preserve general registers, so all of them can be used to pass
+ // arguments except
+ // - RBP frame pointer
KanRobe
https://github.com/KanRobert approved this pull request.
https://github.com/llvm/llvm-project/pull/75580
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KanRobert wrote:
cc @FreddyLeaf
https://github.com/llvm/llvm-project/pull/77525
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https://github.com/KanRobert approved this pull request.
https://github.com/llvm/llvm-project/pull/77525
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@@ -1056,6 +1056,23 @@ def CC_Intel_OCL_BI : CallingConv<[
CCDelegateTo
]>;
+def CC_X86_64_Preserve_None : CallingConv<[
+ // We don't preserve general registers, so all of them can be used to pass
+ // arguments except
+ // - RBPframe pointer
+ // - R10
https://github.com/KanRobert commented:
Past the link of GCC files in description?
https://github.com/llvm/llvm-project/pull/80815
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@@ -1845,6 +1845,7 @@ bool sys::getHostCPUFeatures(StringMap &Features) {
Features["prefetchi"] = HasLeaf7Subleaf1 && ((EDX >> 14) & 1);
Features["usermsr"] = HasLeaf7Subleaf1 && ((EDX >> 15) & 1);
Features["avx10.1-256"] = HasLeaf7Subleaf1 && ((EDX >> 19) & 1);
+ Feat
@@ -1845,6 +1845,7 @@ bool sys::getHostCPUFeatures(StringMap &Features) {
Features["prefetchi"] = HasLeaf7Subleaf1 && ((EDX >> 14) & 1);
Features["usermsr"] = HasLeaf7Subleaf1 && ((EDX >> 15) & 1);
Features["avx10.1-256"] = HasLeaf7Subleaf1 && ((EDX >> 19) & 1);
+ Feat
@@ -462,12 +462,12 @@ TARGET_BUILTIN(__builtin_ia32_blendvps256,
"V8fV8fV8fV8f", "ncV:256:", "avx")
TARGET_BUILTIN(__builtin_ia32_shufpd256, "V4dV4dV4dIi", "ncV:256:", "avx")
TARGET_BUILTIN(__builtin_ia32_shufps256, "V8fV8fV8fIi", "ncV:256:", "avx")
TARGET_BUILTIN(__builtin_ia
KanRobert wrote:
My understanding is that you change the required feature of
__builtin_ia32_cmp[p|s][s|d] from avx to sse for some condition codes. The
title is not accurate.
https://github.com/llvm/llvm-project/pull/84136
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@@ -2613,6 +2614,24 @@ void CGBuilderInserter::InsertHelper(
// called function.
void CodeGenFunction::checkTargetFeatures(const CallExpr *E,
const FunctionDecl *TargetDecl) {
+ // SemaCheking cannot handle below x86 builtins because t
@@ -2613,6 +2614,24 @@ void CGBuilderInserter::InsertHelper(
// called function.
void CodeGenFunction::checkTargetFeatures(const CallExpr *E,
const FunctionDecl *TargetDecl) {
+ // SemaCheking cannot handle below x86 builtins because t
@@ -2613,6 +2614,24 @@ void CGBuilderInserter::InsertHelper(
// called function.
void CodeGenFunction::checkTargetFeatures(const CallExpr *E,
const FunctionDecl *TargetDecl) {
+ // SemaCheking cannot handle below x86 builtins because t
KanRobert wrote:
Still not understand. Shouldn't the target feature of the caller be passed to
the intrinsic when checking the argument of the intrinsic?
https://github.com/llvm/llvm-project/pull/84136
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KanRobert wrote:
> > Still not understand. Shouldn't the target feature of the caller be passed
> > to the intrinsic when checking the argument of the intrinsic?
>
> The target features passing from option can be passed to Semachecking. It's
> special for attribute_target, which is handled in
https://github.com/KanRobert approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/84136
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@@ -217,10 +217,11 @@ enum ProcessorFeatures {
FEATURE_SM3,
FEATURE_SHA512,
FEATURE_SM4,
- // FEATURE_APX_F,
- FEATURE_USERMSR = 112,
- // FEATURE_AVX10_1_256,
- // FEATURE_AVX10_1_512,
+ //FIXME: gcc used string "apxf" instead of "egpr"
KanRobert wr
@@ -173,85 +173,86 @@ X86_FEATURE_COMPAT(AVX512VNNI, "avx512vnni",
34)
X86_FEATURE_COMPAT(AVX512BITALG,"avx512bitalg", 35)
X86_FEATURE_COMPAT(AVX512BF16, "avx512bf16",36)
X86_FEATURE_COMPAT(AVX512VP2INTERSECT, "avx512vp2intersect",
@@ -1845,6 +1845,7 @@ bool sys::getHostCPUFeatures(StringMap &Features) {
Features["prefetchi"] = HasLeaf7Subleaf1 && ((EDX >> 14) & 1);
Features["usermsr"] = HasLeaf7Subleaf1 && ((EDX >> 15) & 1);
Features["avx10.1-256"] = HasLeaf7Subleaf1 && ((EDX >> 19) & 1);
+ Feat
@@ -248,10 +248,11 @@ X86_FEATURE_COMPAT(AVXVNNIINT16,"avxvnniint16",
0)
X86_FEATURE_COMPAT(SM3, "sm3",0)
X86_FEATURE_COMPAT(SHA512, "sha512", 0)
X86_FEATURE_COMPAT(SM4, "sm4",
KanRobert wrote:
Thanks for this!
https://github.com/llvm/llvm-project/pull/77925
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KanRobert wrote:
Why not return `i32` for 64-bit mask in 32-bit mode?
https://github.com/llvm/llvm-project/pull/77733
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KanRobert wrote:
> > Why not return `i32` for 64-bit mask in 32-bit mode?
>
> You mean in two `i32` registers? The problem is the inline asm constraint has
> 1:1 map with physical register except corner cases. And represent a `k`
> constraint into two GPR registers is inefficient.
Is it repre
@@ -57046,17 +57046,17 @@ X86TargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
// in the normal allocation?
case 'k':
if (Subtarget.hasAVX512()) {
-if (VT == MVT::i1)
+if (VT == MVT::v1i1 || VT == MVT::i1)
re
@@ -57046,17 +57046,17 @@ X86TargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
// in the normal allocation?
case 'k':
if (Subtarget.hasAVX512()) {
-if (VT == MVT::i1)
+if (VT == MVT::v1i1 || VT == MVT::i1)
re
https://github.com/KanRobert created
https://github.com/llvm/llvm-project/pull/78901
None
>From 6e490075f52d8b8cefcdde59fe24914b80a64039 Mon Sep 17 00:00:00 2001
From: Shengchen Kan
Date: Sun, 21 Jan 2024 22:02:21 +0800
Subject: [PATCH] [X86][Driver] Enable feature ndd for -mapxf
---
clang/i
@@ -803,10 +803,10 @@
// RUN: %clang -target x86_64-unknown-unknown -march=x86-64 -mapx-features=ndd
-x c -E -dM -o - %s | FileCheck --check-prefix=NDD %s
// RUN: %clang -target x86_64-unknown-unknown -march=x86-64
-mapx-features=ccmp -x c -E -dM -o - %s | FileCheck --check-pr
@@ -803,10 +803,10 @@
// RUN: %clang -target x86_64-unknown-unknown -march=x86-64 -mapx-features=ndd
-x c -E -dM -o - %s | FileCheck --check-prefix=NDD %s
// RUN: %clang -target x86_64-unknown-unknown -march=x86-64
-mapx-features=ccmp -x c -E -dM -o - %s | FileCheck --check-pr
@@ -803,10 +803,10 @@
// RUN: %clang -target x86_64-unknown-unknown -march=x86-64 -mapx-features=ndd
-x c -E -dM -o - %s | FileCheck --check-prefix=NDD %s
// RUN: %clang -target x86_64-unknown-unknown -march=x86-64
-mapx-features=ccmp -x c -E -dM -o - %s | FileCheck --check-pr
https://github.com/KanRobert edited
https://github.com/llvm/llvm-project/pull/78901
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KanRobert wrote:
Thanks! @phoebewang
https://github.com/llvm/llvm-project/pull/78901
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Author: Shengchen Kan
Date: 2021-11-05T09:11:41+08:00
New Revision: be08e452f36602cd73f816787bf16d1a0405ff09
URL:
https://github.com/llvm/llvm-project/commit/be08e452f36602cd73f816787bf16d1a0405ff09
DIFF:
https://github.com/llvm/llvm-project/commit/be08e452f36602cd73f816787bf16d1a0405ff09.diff
https://github.com/KanRobert approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/66310
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https://github.com/KanRobert approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/68944
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@@ -1223,6 +1223,12 @@ __m256i test_mm256_stream_load_si256(__m256i const *a) {
return _mm256_stream_load_si256(a);
}
+__m256i test_mm256_stream_load_si256_const(void const *a) {
KanRobert wrote:
+1
https://github.com/llvm/llvm-project/pull/66310
_
Author: Shengchen Kan
Date: 2020-02-24T13:45:27+08:00
New Revision: 6a3506a208b90e65c719b0942376f46902a08945
URL:
https://github.com/llvm/llvm-project/commit/6a3506a208b90e65c719b0942376f46902a08945
DIFF:
https://github.com/llvm/llvm-project/commit/6a3506a208b90e65c719b0942376f46902a08945.diff
Author: Shengchen Kan
Date: 2020-03-12T09:26:51+08:00
New Revision: 560aa53f8fe58abcbc4bb441b631e8a401ee78fe
URL:
https://github.com/llvm/llvm-project/commit/560aa53f8fe58abcbc4bb441b631e8a401ee78fe
DIFF:
https://github.com/llvm/llvm-project/commit/560aa53f8fe58abcbc4bb441b631e8a401ee78fe.diff
Author: Shengchen Kan
Date: 2020-03-12T10:03:41+08:00
New Revision: ab69cd0779c529519eb7d26e0fa1b8dfb505f838
URL:
https://github.com/llvm/llvm-project/commit/ab69cd0779c529519eb7d26e0fa1b8dfb505f838
DIFF:
https://github.com/llvm/llvm-project/commit/ab69cd0779c529519eb7d26e0fa1b8dfb505f838.diff
Author: Shengchen Kan
Date: 2020-03-12T10:56:39+08:00
New Revision: 214d24e1f8e0737a5aa2e2c52a1ae095fb1c1abd
URL:
https://github.com/llvm/llvm-project/commit/214d24e1f8e0737a5aa2e2c52a1ae095fb1c1abd
DIFF:
https://github.com/llvm/llvm-project/commit/214d24e1f8e0737a5aa2e2c52a1ae095fb1c1abd.diff
@@ -983,6 +983,8 @@ static void getAvailableFeatures(unsigned ECX, unsigned
EDX, unsigned MaxLeaf,
setFeature(FEATURE_USERMSR);
if (HasLeaf7Subleaf1 && ((EDX >> 19) & 1))
setFeature(FEATURE_AVX10_1_256);
+ if (HasLeaf7Subleaf1 && ((EDX >> 21) & 1))
@@ -265,6 +265,7 @@ X86_MICROARCH_LEVEL(X86_64_BASELINE,"x86-64",
95)
X86_MICROARCH_LEVEL(X86_64_V2, "x86-64-v2",96)
X86_MICROARCH_LEVEL(X86_64_V3, "x86-64-v3",97)
X86_MICROARCH_LEVEL(X86_64_V4, "x86-64-v4",98)
+
@@ -219,6 +219,7 @@
#define bit_PREFETCHI 0x4000
#define bit_USERMSR 0x8000
#define bit_AVX10 0x0008
+#define bit_APXF 0x0020
KanRobert wrote:
Where is the number from? Add the link in your description of the PR.
htt
@@ -265,6 +265,7 @@ X86_MICROARCH_LEVEL(X86_64_BASELINE,"x86-64",
95)
X86_MICROARCH_LEVEL(X86_64_V2, "x86-64-v2",96)
X86_MICROARCH_LEVEL(X86_64_V3, "x86-64-v3",97)
X86_MICROARCH_LEVEL(X86_64_V4, "x86-64-v4",98)
+
https://github.com/KanRobert approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/80636
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https://github.com/KanRobert created
https://github.com/llvm/llvm-project/pull/97525
None
>From 1aab0a95629371c61273c80f6335a6723c7d27c4 Mon Sep 17 00:00:00 2001
From: Shengchen Kan
Date: Wed, 3 Jul 2024 11:30:47 +0800
Subject: [PATCH] [Driver][X86] Add flang visibility for -mapx-features=
--
https://github.com/KanRobert edited
https://github.com/llvm/llvm-project/pull/97525
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KanRobert wrote:
Also, AArch64 also exposes the tuning flag `msve-vector-bits=` to flang.
https://github.com/llvm/llvm-project/pull/97525
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https://github.com/KanRobert updated
https://github.com/llvm/llvm-project/pull/97525
>From 1aab0a95629371c61273c80f6335a6723c7d27c4 Mon Sep 17 00:00:00 2001
From: Shengchen Kan
Date: Wed, 3 Jul 2024 11:30:47 +0800
Subject: [PATCH 1/2] [Driver][X86] Add flang visibility for -mapx-features=
---
https://github.com/KanRobert closed
https://github.com/llvm/llvm-project/pull/97525
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@@ -749,6 +749,11 @@ def TuningUseGLMDivSqrtCosts
: SubtargetFeature<"use-glm-div-sqrt-costs", "UseGLMDivSqrtCosts", "true",
"Use Goldmont specific floating point div/sqrt costs">;
+// Starting with Redwood Cove architecture, the branch has branch taken hint
+// (i
@@ -749,6 +749,11 @@ def TuningUseGLMDivSqrtCosts
: SubtargetFeature<"use-glm-div-sqrt-costs", "UseGLMDivSqrtCosts", "true",
"Use Goldmont specific floating point div/sqrt costs">;
+// Starting with Redwood Cove architecture, the branch has branch taken hint
+// (i
@@ -0,0 +1,95 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-linux -branch-hint
-branch-hint-probability-threshold=60 -show-mc-encoding | FileCheck %s
+
+; Design: Insert "ds # encoding: [0x3e]" for condition bra
@@ -0,0 +1,95 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-linux -branch-hint
-branch-hint-probability-threshold=60 -show-mc-encoding | FileCheck %s
+
+; Design: Insert "ds # encoding: [0x3e]" for condition bra
@@ -0,0 +1,95 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-linux -branch-hint
-branch-hint-probability-threshold=60 -show-mc-encoding | FileCheck %s
+
+; Design: Insert "ds # encoding: [0x3e]" for condition bra
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