@@ -0,0 +1,494 @@
+//===-- RISCVSchedGenericOOO.td - Generic O3 Processor -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
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@@ -623,13 +623,37 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo
&TI,
}
}
+ auto checkVsetvl = [&](unsigned SEWOffset,
+unsigned LMULOffset) -> bool {
+const FunctionDecl *FD = SemaRef.getCurFunctionDecl();
+
@@ -623,13 +623,37 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo
&TI,
}
}
+ auto checkVsetvl = [&](unsigned SEWOffset,
wangpc-pp wrote:
checkVsetvl -> CheckVSetVL? At least the first letter should be capital.
https://github.com/llvm/llv
@@ -623,13 +623,37 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo
&TI,
}
}
+ auto checkVsetvl = [&](unsigned SEWOffset,
wangpc-pp wrote:
I think it is a variable, most lambdas in tree are capital. :-)
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@@ -22,11 +24,21 @@
// uses the record name by replacing Feature with Has.
// value - Value to assign to the field in RISCVSubtarget when this
// extension is enabled. Usually "true", but can be changed.
-class RISCVExtension implies = [],
@@ -22,11 +22,20 @@
// uses the record name by replacing Feature with Has.
// value - Value to assign to the field in RISCVSubtarget when this
// extension is enabled. Usually "true", but can be changed.
-class RISCVExtension implies = [],
@@ -22,11 +22,20 @@
// uses the record name by replacing Feature with Has.
// value - Value to assign to the field in RISCVSubtarget when this
// extension is enabled. Usually "true", but can be changed.
-class RISCVExtension implies = [],
@@ -12,21 +12,32 @@
// Subclass of SubtargetFeature to be used when the feature is also a RISC-V
// extension. Extensions have a version and may be experimental.
+// NOTE: The extension name must start with
+// - "FeatureStdExt" for standard extensions
+// - "Featu
@@ -1477,6 +1477,10 @@ def TuneConditionalCompressedMoveFusion
def HasConditionalMoveFusion :
Predicate<"Subtarget->hasConditionalMoveFusion()">;
def NoConditionalMoveFusion :
Predicate<"!Subtarget->hasConditionalMoveFusion()">;
+def TuneMIPSP8700
+: SubtargetFeature<"m
@@ -12,21 +12,32 @@
// Subclass of SubtargetFeature to be used when the feature is also a RISC-V
// extension. Extensions have a version and may be experimental.
+// NOTE: The extension name must start with
+// - "FeatureStdExt" for standard extensions
+// - "Featu
@@ -12,21 +12,32 @@
// Subclass of SubtargetFeature to be used when the feature is also a RISC-V
// extension. Extensions have a version and may be experimental.
+// NOTE: The extension name must start with
+// - "FeatureStdExt" for standard extensions
+// - "Featu
https://github.com/wangpc-pp approved this pull request.
LGTM. Nice refactor!
https://github.com/llvm/llvm-project/pull/120040
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wangpc-pp wrote:
> Fails buildbot:
> https://lab.llvm.org/buildbot/#/builders/24/builds/2791/steps/10/logs/stdio
>
> ```
> -- Testing: 83950 of 83951 tests, 48 workers --
> Testing: 0.. 10..
> FAIL: Clang :: Preprocessor/has_builtin_cpuid.c (15996 of 83950)
> TEST 'Clang :
@@ -842,6 +842,12 @@ def HasStdExtH : Predicate<"Subtarget->hasStdExtH()">,
AssemblerPredicate<(all_of FeatureStdExtH),
"'H' (Hypervisor)">;
+// Debugger extensions
wangpc-pp wrote:
They are also `Superviso
wangpc-pp wrote:
> > I thought the P550 was supposed to support RV64GCB, but that would require
> > Zbs support, which isn't listed here.
>
> The P550 version in the HiFive Premier board does not support Zbs. ISA string
> from /proc/cpuinfo is `rv64imafdch_zicsr_zifencei_zba_zbb_sscofpmf`
Tha
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/124239
>From 2ce077b011a9dcac0f9649493a50819971695b73 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Tue, 16 Jul 2024 16:08:16 +0800
Subject: [PATCH 1/2] [RISCV][MC] Support Zvabd instructions
Support of these
https://github.com/wangpc-pp created
https://github.com/llvm/llvm-project/pull/124239
**NOTE: This is an early-access support only for evaluation, not going to be
merged and may be changable during the process of fast-track proposal.**
This PR contains the MC/CodeGen support of ByteDance
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>From 2ce077b011a9dcac0f9649493a50819971695b73 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Tue, 16 Jul 2024 16:08:16 +0800
Subject: [PATCH 1/2] [RISCV][MC] Support Zvabd instructions
Support of these
@@ -553,6 +553,37 @@ def XIANGSHAN_NANHU :
RISCVProcessorModel<"xiangshan-nanhu",
TuneZExtWFusion,
TuneShiftedZExtWFusion]>;
+def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunmi
https://github.com/wangpc-pp approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/122164
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@@ -553,6 +553,37 @@ def XIANGSHAN_NANHU :
RISCVProcessorModel<"xiangshan-nanhu",
TuneZExtWFusion,
TuneShiftedZExtWFusion]>;
+def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunmi
https://github.com/wangpc-pp edited
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@@ -0,0 +1,494 @@
+//===-- RISCVSchedGenericOOO.td - Generic O3 Processor -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
https://github.com/wangpc-pp edited
https://github.com/llvm/llvm-project/pull/96283
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wangpc-pp wrote:
Ping. Any more comments?
https://github.com/llvm/llvm-project/pull/120712
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https://github.com/wangpc-pp approved this pull request.
I'd like to give it a LGTM. :-)
https://github.com/llvm/llvm-project/pull/132259
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@@ -519,6 +517,9 @@ struct RVVIntrinsicRecord {
// e.g. vadd
const char *OverloadedName;
+ // Required target features for this intrinsic.
+ uint32_t RequiredExtensions[(RVV_REQ_NUM + 31) / 32];
wangpc-pp wrote:
I wonder if we can use `FeatureBitset` he
@@ -45,7 +45,7 @@ struct SemaRecord {
unsigned Log2LMULMask;
// Required extensions for this intrinsic.
- uint32_t RequiredExtensions;
+ uint32_t RequiredExtensions[(RVV_REQ_Experimental + 31) / 32];
wangpc-pp wrote:
RVV_REQ_Experimental->RVV_REQ_NUM?
@@ -176,6 +176,13 @@ def HasStdExtZicfiss :
Predicate<"Subtarget->hasStdExtZicfiss()">,
"'Zicfiss' (Shadow stack)">;
def NoHasStdExtZicfiss : Predicate<"!Subtarget->hasStdExtZicfiss()">;
+def FeatureStdExtZilsd
+: RISCVExtension<1
https://github.com/wangpc-pp approved this pull request.
https://github.com/llvm/llvm-project/pull/131261
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@@ -19,31 +19,29 @@
# TODO: more exhaustive testing of immediate encoding.
-# CHECK-ASM-AND-OBJ: c.ldsp ra, 0(sp)
-# CHECK-ASM: encoding: [0x82,0x60]
+# CHECK-ASM-AND-OBJ: c.ldsp s0, 0(sp)
+# CHECK-ASM: encoding: [0x02,0x64]
# CHECK-NO-EXT: error: instruction requires the f
https://github.com/wangpc-pp commented:
Please add a ReleaseNote.
https://github.com/llvm/llvm-project/pull/131094
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@@ -176,6 +176,13 @@ def HasStdExtZicfiss :
Predicate<"Subtarget->hasStdExtZicfiss()">,
"'Zicfiss' (Shadow stack)">;
def NoHasStdExtZicfiss : Predicate<"!Subtarget->hasStdExtZicfiss()">;
+def FeatureStdExtZilsd
+: RISCVExtension<1
https://github.com/wangpc-pp approved this pull request.
https://github.com/llvm/llvm-project/pull/132529
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@@ -830,3 +830,16 @@ def : RISCVRegisterClass<[XLenVT], 32, (add
SF_VCIX_STATE)> {
let RegInfos = XLenRI;
let isAllocatable = 0;
}
+
+//===--===//
+// XSfmmbase tiles
+//===
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/133710
>From 81c45d6226d217197ae7b6c35e9ace22027cb7a5 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Mon, 31 Mar 2025 20:12:40 +0800
Subject: [PATCH 1/2] [RISCV][NFC] Make generated intrinsic records more
human
@@ -558,6 +558,34 @@ def XIANGSHAN_NANHU :
RISCVProcessorModel<"xiangshan-nanhu",
TuneZExtWFusion,
TuneShiftedZExtWFusion]>;
+def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunmi
https://github.com/wangpc-pp approved this pull request.
LGTM! Thanks for the insistence!
https://github.com/llvm/llvm-project/pull/123193
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https://github.com/llvm/llvm-project/pull/135647
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wangpc-pp wrote:
LGTM in general, but I have a question here: can you clarify the naming
strategy? The name used in `-mcpu` is `xiangshan-kunminghu`, which corresponds
to the `V2R2` version now apparently. Then, will there be `V2R3`/`V3R2`/...? If
so, what should we use in `-mcpu`?
https://gi
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https://github.com/wangpc-pp commented:
Release notes?
https://github.com/llvm/llvm-project/pull/136694
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https://github.com/wangpc-pp approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/136670
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wangpc-pp wrote:
/cherry-pick 6c3373534305a2ce23dd939344dd0a387a09fe88
https://github.com/llvm/llvm-project/pull/136842
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@@ -167,6 +167,7 @@ Changes to the RISC-V Backend
* Adds assembler support for ``.option exact``, which disables automatic
compression,
and branch and linker relaxation. This can be disabled with ``.option
noexact``,
which is also the default.
+* Support was added for the
https://github.com/wangpc-pp created
https://github.com/llvm/llvm-project/pull/136842
This matches GCC and we supported it in LLVM 17/18.
Fixes #136803
>From e133a5fc0091ec045a0ea0114d553c72e8f33e51 Mon Sep 17 00:00:00 2001
From: Pengcheng Wang
Date: Wed, 23 Apr 2025 18:19:41 +0800
Subject:
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/136842
>From 723976e74398e12252a599e3aabb05ec8f2515ab Mon Sep 17 00:00:00 2001
From: Pengcheng Wang
Date: Wed, 23 Apr 2025 18:19:41 +0800
Subject: [PATCH 1/4] [RISCV] Allow `Zicsr`/`Zifencei` to duplicate with `g`
T
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/136842
>From 723976e74398e12252a599e3aabb05ec8f2515ab Mon Sep 17 00:00:00 2001
From: Pengcheng Wang
Date: Wed, 23 Apr 2025 18:19:41 +0800
Subject: [PATCH] [RISCV] Allow `Zicsr`/`Zifencei` to duplicate with `g`
This
https://github.com/wangpc-pp approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/136832
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https://github.com/llvm/llvm-project/pull/137941
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wangpc-pp wrote:
ping.
https://github.com/llvm/llvm-project/pull/133710
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wangpc-pp wrote:
> Does this have any effect on the build time of the compiler? This file is
> already large and I assume this significantly increases the size.
Yes, the .inc size is 6 times larger. I don't know how to assess the impact,
theoretically the time to read file and tokenize will in
wangpc-pp wrote:
> @wangpc-pp you might want to revert this or fix it soon.
Reverted. Thanks!
https://github.com/llvm/llvm-project/pull/133710
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https://github.com/llvm/llvm-project/pull/133710
>From 031ef3fa34f0448dc9743135802e7c6be2025442 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Mon, 31 Mar 2025 20:12:40 +0800
Subject: [PATCH 1/3] [RISCV][NFC] Make generated intrinsic records more
human
https://github.com/wangpc-pp closed
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@@ -126,6 +126,7 @@ Changes to the PowerPC Backend
Changes to the RISC-V Backend
-
+
wangpc-pp wrote:
Remove this extra blank line.
https://github.com/llvm/llvm-project/pull/123193
___
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@@ -558,6 +558,34 @@ def XIANGSHAN_NANHU :
RISCVProcessorModel<"xiangshan-nanhu",
TuneZExtWFusion,
TuneShiftedZExtWFusion]>;
+def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunmi
@@ -558,6 +558,34 @@ def XIANGSHAN_NANHU :
RISCVProcessorModel<"xiangshan-nanhu",
TuneZExtWFusion,
TuneShiftedZExtWFusion]>;
+def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunmi
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/136842
>From 723976e74398e12252a599e3aabb05ec8f2515ab Mon Sep 17 00:00:00 2001
From: Pengcheng Wang
Date: Wed, 23 Apr 2025 18:19:41 +0800
Subject: [PATCH 1/5] [RISCV] Allow `Zicsr`/`Zifencei` to duplicate with `g`
T
wangpc-pp wrote:
According to the sync-up meeting, we can proceed this patch as-is. I will merge
this in a few days.
I added back the release note. @asb
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@@ -365,6 +365,32 @@ def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670",
SiFiveP600Model,
TuneVXRMPipelineFlush,
TunePostRAScheduler]>;
+def SIFIVE_P870 : RISCVProcessorModel<"sifive-p870", NoSched
wangpc-pp wrote:
I am kind of confused now. So the situation here is that RVIOS has already
implemented these vendor extensions in cores and RVIOS is also trying to make
these extensions official RVI standards, right?
https://github.com/llvm/llvm-project/pull/127694
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wangpc-pp wrote:
> LLVM Buildbot has detected a new failure on builder `flang-x86_64-windows`
> running on `minipc-ryzen-win` while building `clang,llvm` at step 7
> "test-build-unified-tree-check-flang".
>
> Full details are available at:
> https://lab.llvm.org/buildbot/#/builders/166/builds
wangpc-pp wrote:
Agree, we should try the RISCVInsertVSETVLI approach.
https://github.com/llvm/llvm-project/pull/128636
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https://github.com/wangpc-pp approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/126064
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wangpc-pp wrote:
I am not familiar with the target attribute implementation, can we get the list
of function features here and add the clobbers at:
https://github.com/llvm/llvm-project/blob/6d93280aabc2fd132f54e5aa615d25abeadabe7b/clang/lib/CodeGen/CGStmt.cpp#L3087-L3093
cc @topperc @4vtomat
wangpc-pp wrote:
> > I am not familiar with the target attribute implementation, can we get the
> > list of function features here and add the clobbers at:
> > https://github.com/llvm/llvm-project/blob/6d93280aabc2fd132f54e5aa615d25abeadabe7b/clang/lib/CodeGen/CGStmt.cpp#L3087-L3093
> >
> > cc
wangpc-pp wrote:
> > I am kind of confused now. So the situation here is that RVIOS has already
> > implemented these vendor extensions in cores and RVIOS is also trying to
> > make these extensions official RVI standards, right?
>
> You're confusing two things. We (Rivos) have defined a set o
@@ -68,7 +68,7 @@ class RISCVTargetInfo : public TargetInfo {
return TargetInfo::VoidPtrBuiltinVaList;
}
- std::string_view getClobbers() const override { return ""; }
+ std::string_view getClobbers() const override { return "~{vl},~{vtype}"; }
wangpc-
https://github.com/wangpc-pp commented:
I see. But what's the difference if we add `vl/vtype` to the list of clobbered
registers explicitly in C/C++ asm statements?
https://github.com/llvm/llvm-project/pull/128636
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wangpc-pp wrote:
> I think what @wangpc-pp advocated here (please correct me if I'm wrong) was
> that user should be responsible annotating these registers as clobbered so
> that we have more freedom on scheduling when the inline assembly is not using
> any vector instructions. While other app
https://github.com/wangpc-pp commented:
I think you should provide LLVM IR tests in
`llvm/test/Transforms/LoopVectorize/**` instead of Clang tests.
https://github.com/llvm/llvm-project/pull/131781
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@@ -962,6 +962,8 @@ RISCVTargetLowering::RISCVTargetLowering(const
TargetMachine &TM,
static const unsigned ZvfhminZvfbfminPromoteOps[] = {
ISD::FMINNUM,
ISD::FMAXNUM,
+ISD::FMINIMUMNUM,
wangpc-pp wrote:
RISCV changes should be in
@@ -0,0 +1,1059 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --version 5
+; RUN: opt --passes=loop-vectorize --mtriple=riscv64 -mattr="+zvfh,+v" -S < %s
| FileCheck %s --check-prefix=RV64
+; RUN: opt --passes=loop-vectorize --mtriple=aa
https://github.com/wangpc-pp created
https://github.com/llvm/llvm-project/pull/133710
We add comment markers and print enum names instead of numbers.
For required extensions, we print the feature list instead of raw
bits.
>From 81c45d6226d217197ae7b6c35e9ace22027cb7a5 Mon Sep 17 00:00:00 2001
wangpc-pp wrote:
Examples:
```cpp
{/*Name=*/"vbrev_v", /*OverloadedName=*/"vbrev",
/*RequiredExtensions=*/{RVV_REQ_Zvbb}, /*PrototypeIndex=*/417,
/*SuffixIndex=*/47, /*OverloadedSuffixIndex=*/0, /*PrototypeLength=*/2,
/*SuffixLength=*/1, /*OverloadedSuffixSize=*/0, /*TypeRangeMask=*/15,
/*Log
@@ -0,0 +1,1059 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --version 5
wangpc-pp wrote:
Precommit this test.
https://github.com/llvm/llvm-project/pull/131781
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https://github.com/wangpc-pp approved this pull request.
https://github.com/llvm/llvm-project/pull/132676
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wangpc-pp wrote:
> > but won't merge them until they are ratified just like Zvzip/Zvabd/Zibimm
>
> I think this patch is supported to be the vendor instruction set of `SiFive
> Xsfmm* Attached Matrix Extensions` if I understand correctly of this PR.
>
> AME is another issue that we don’t have
https://github.com/wangpc-pp commented:
Thanks! The PR is neater now! Please add a ReleaseNote as well.
https://github.com/llvm/llvm-project/pull/139369
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@@ -0,0 +1,153 @@
+//===-- RISCVInstrInfoQ.td - RISC-V 'Q' instructions ---*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -131,20 +131,22 @@ def FPR32INX : RegisterOperand {
// The DAGOperand can be unset if the predicates are not enough to define it.
class ExtInfo predicates,
ValueType primaryvt, DAGOperand primaryty, DAGOperand f32ty,
- DAGOperand f64ty, DAGOperand
https://github.com/wangpc-pp edited
https://github.com/llvm/llvm-project/pull/139369
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https://github.com/wangpc-pp approved this pull request.
https://github.com/llvm/llvm-project/pull/138827
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@@ -43,34 +43,43 @@ def WriteAtomicSTD : SchedWrite;// Atomic store double
word
def WriteFAdd16 : SchedWrite;// 16-bit floating point
addition/subtraction
def WriteFAdd32 : SchedWrite;// 32-bit floating point
addition/subtraction
def WriteFAdd64 : Sc
https://github.com/wangpc-pp edited
https://github.com/llvm/llvm-project/pull/139369
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@@ -131,20 +131,22 @@ def FPR32INX : RegisterOperand {
// The DAGOperand can be unset if the predicates are not enough to define it.
class ExtInfo predicates,
ValueType primaryvt, DAGOperand primaryty, DAGOperand f32ty,
- DAGOperand f64ty, DAGOperand
https://github.com/wangpc-pp commented:
We should support `Zfa+Q` as well (this can be a follow-up).
https://github.com/llvm/llvm-project/pull/139369
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@@ -75,7 +75,7 @@ def ZhinxminZdinxExt: ExtInfo<"_INX", "Zfinx",
?, ?, FPR32INX, FPR64INX, FPR16INX>;
def ZhinxZdinx32Ext : ExtInfo<"_IN32X", "ZdinxGPRPairRV32",
[HasStdExtZhinx, HasStdExtZdinx, IsRV32]
https://github.com/wangpc-pp approved this pull request.
LGTM with nits.
https://github.com/llvm/llvm-project/pull/139519
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