https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/112747
>From 8a29c58a9034bd9123a26448607e751ee9a6d658 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Thu, 17 Oct 2024 14:04:05 +0100
Subject: [PATCH 1/6] [Clang][AArch64] Fix Pure Scalables Types argument
@@ -303,6 +368,20 @@ AArch64ABIInfo::classifyArgumentType(QualType Ty, bool
IsVariadic,
if (EIT->getNumBits() > 128)
return getNaturalAlignIndirect(Ty, false);
+if (const BuiltinType *BT = Ty->getAs()) {
+ if (BT->isSVEBool() || BT->isSVECount())
+
@@ -200,7 +200,7 @@ SVE_PREDICATE_TYPE_ALL("__clang_svboolx4_t", "svboolx4_t",
SveBoolx4, SveBoolx4T
SVE_OPAQUE_TYPE("__SVCount_t", "__SVCount_t", SveCount, SveCountTy)
-AARCH64_VECTOR_TYPE_MFLOAT("__MFloat8_t", "__MFloat8_t", MFloat8, MFloat8Ty,
1, 8, 1)
+AARCH64_VECTOR_TY
momchil-velikov wrote:
> Are you also planning to do the feature test macros, e.g. `__ARM_FEATURE_FP8`?
In principle, yes, but once the ACLE intrinsics are implemented, since the
presence of the macro indicates that
both target feature *and* the intrinsics are available.
https://github.com/llv
momchil-velikov wrote:
Thanks for the reviews, much appreciated!
https://github.com/llvm/llvm-project/pull/112747
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>From c2f223d84c18498f3cbe1582b006b0d4c52999aa Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Thu, 17 Oct 2024 14:04:05 +0100
Subject: [PATCH 1/5] [Clang][AArch64] Fix Pure Scalables Types argument
@@ -0,0 +1,338 @@
+// RUN: %clang_cc1 -O3 -triple aarch64
-target-feature +sve -target-feature +sve2p1 -mvscale-min=1 -mvscale-max=1
-emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,CHECK-AAPCS
+// RUN: %clang_cc1 -O3 -triple arm64-apple-
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https://github.com/momchil-velikov created
https://github.com/llvm/llvm-project/pull/112747
Pure Scalable Types are defined in AAPCS64 here:
https://github.com/ARM-software/abi-aa/blob/main/aapcs64/aapcs64.rst#pure-scalable-types-psts
And should be passed according to Rule C.7 here:
https
https://github.com/momchil-velikov created
https://github.com/llvm/llvm-project/pull/118124
None
>From 3a9643e6c2d61eae2e23df42c19b1410d4a5fcc5 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Thu, 21 Nov 2024 11:21:29 +
Subject: [PATCH 1/2] FP8 CVT/CVTL
---
clang/include/clang/Basic
https://github.com/momchil-velikov created
https://github.com/llvm/llvm-project/pull/118125
None
>From 3a9643e6c2d61eae2e23df42c19b1410d4a5fcc5 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Thu, 21 Nov 2024 11:21:29 +
Subject: [PATCH 1/3] FP8 CVT/CVTL
---
clang/include/clang/Basic
https://github.com/momchil-velikov created
https://github.com/llvm/llvm-project/pull/118123
None
>From 3a9643e6c2d61eae2e23df42c19b1410d4a5fcc5 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Thu, 21 Nov 2024 11:21:29 +
Subject: [PATCH] FP8 CVT/CVTL
---
clang/include/clang/Basic/arm
@@ -11182,6 +11182,10 @@ Value
*CodeGenFunction::EmitAArch64SMEBuiltinExpr(unsigned BuiltinID,
BuiltinID == SME::BI__builtin_sme_svstr_za)
return EmitSMELdrStr(TypeFlags, Ops, Builtin->LLVMIntrinsic);
+ // Emit set FPMR for intrinsics that require it
-
@@ -0,0 +1,48 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 2
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2,+fp8 -verify-machineinstrs
-force-streaming < %s | FileCheck %s
+
+; F1CVTL / F2CVTL
+
+define { , } @f1cvtl
momchil-velikov wrote:
We would also need TargetGuard tests, e.g.
`/clang/test/Sema/aarch64-sme2-intrinsics`.
https://github.com/llvm/llvm-project/pull/116959
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@@ -305,6 +305,21 @@ multiclass sme_outer_product_fp32 sz,
ZPRRegOp zpr_ty, string mne
def : SME_ZA_Tile_TwoPred_TwoVec_Pat;
}
+multiclass sme2_fp8_fmopa_za32 {
+def NAME : sme_fp_outer_product_inst<0, 0b01, 0b00, TileOp32, ZPR8,
mnemonic>, SMEPseudo2Instr {
+ bit
https://github.com/momchil-velikov created
https://github.com/llvm/llvm-project/pull/118961
The fix for passing Pure Scalable Types
(https://github.com/llvm/llvm-project/pull/112747) was incomplete,
it didn't handle correctly tuples of SVE vectors (e.g. `sveboolx2_t`,
`svfloat32x4_t`, etc).
T
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* The FP8 scalar type (`__mfp8`) was described as a vector type
* The FP8 vector types were described/assumed to have
integer element type (the element type ought to be `__mfp8`),
* Add
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@@ -10753,10 +10758,45 @@ class sve2_fp8_down_cvt_single opc, string
mnemonic,
let Inst{5} = 0b0;
let Inst{4-0} = Zd;
let Uses = [FPMR, FPCR];
+
+ let mayLoad = 1;
+ let mayStore = 0;
}
-multiclass sve2_fp8_down_cvt_single opc, string mnemonic,
RegisterOperand src
@@ -0,0 +1,101 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 5
+// RUN: %clang_cc1-triple aarch64-none-linux-gnu -target-feature +sve
-target-feature +sve2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall
-em
@@ -0,0 +1,33 @@
+// REQUIRES: aarch64-registered-target
+
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve
-target-feature +bf16 -verify -emit-llvm %s
momchil-velikov wrote:
This feature is needed by `svcreate2` and `svundef_bf16`. What p
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@@ -0,0 +1,78 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc -mattr=+bf16,+sve2,+fp8 < %s | FileCheck %s
momchil-velikov wrote:
Removed.
https://github.com/llvm/llvm-project/pull/118123
__
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>From cdd86588c639f818909964ab49b9972da6869cb3 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Thu, 21 Nov 2024 11:21:29 +
Subject: [PATCH 1/3] [AArch64] Implement FP8 SVE intrinsics for widenin
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/118123
>From cdd86588c639f818909964ab49b9972da6869cb3 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Thu, 21 Nov 2024 11:21:29 +
Subject: [PATCH] [AArch64] Implement FP8 SVE intrinsics for widening
c
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/118124
>From cdd86588c639f818909964ab49b9972da6869cb3 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Thu, 21 Nov 2024 11:21:29 +
Subject: [PATCH 1/2] [AArch64] Implement FP8 SVE intrinsics for widenin
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/118125
>From cdd86588c639f818909964ab49b9972da6869cb3 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Thu, 21 Nov 2024 11:21:29 +
Subject: [PATCH 1/4] [AArch64] Implement FP8 SVE intrinsics for widenin
@@ -105,6 +105,7 @@ include "arm_immcheck_incl.td"
// N: svfloat64_t
// $: svbfloat16_t
// ~: svmfloat8_t
+// !: mfloat8_t (splat to svmfloat8_t)
momchil-velikov wrote:
Done
https://github.com/llvm/llvm-project/pull/118125
@@ -10877,24 +10923,37 @@ class sve_fp8_dot_indexed opc, ZPRRegOp
dst_ty, Operand iop_ty, string m
let DestructiveInstType = DestructiveOther;
let hasSideEffects = 0;
let mayRaiseFPException = 1;
+
+ let mayLoad = 1;
+ let mayStore = 0;
}
// FP8 Widening Dot-Produ
@@ -2447,3 +2447,39 @@ let SVETargetGuard = "sve2,faminmax", SMETargetGuard =
"sme2,faminmax" in {
defm SVAMIN : SInstZPZZ<"svamin", "hfd", "aarch64_sve_famin",
"aarch64_sve_famin_u">;
defm SVAMAX : SInstZPZZ<"svamax", "hfd", "aarch64_sve_famax",
"aarch64_sve_famax_u">;
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momchil-velikov wrote:
> > This patch adds instcombine to some tests that were passing
> Can the instcombines be replaced with something simpler like dce or maybe
> instsimplify? It might be OK with just mem2reg.
Unfortunately just `mem2reg` does not cut it. The original issue it that Clang
ge
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momchil-velikov wrote:
> Isn't it a bug that clang reports an incorrect mangled name?
I reckon the mangled name reported by clang is correct in the sense it's the
final symbol name in the assembler/object file.
https://github.com/llvm/llvm-project/pull/121800
@@ -650,6 +655,16 @@ def get_triple_from_march(march):
print("Cannot find a triple. Assume 'x86'", file=sys.stderr)
return "x86"
+def get_global_underscores(raw_tool_output):
+m = DATA_LAYOUT_RE.search(raw_tool_output)
+if not m:
+return False
+data
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/119033
>From db963803f1a84b7deae31330e9c2f74df85a01cd Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Fri, 6 Dec 2024 13:09:23 +
Subject: [PATCH 1/7] [AArch64] Refactor implementation of FP8 types (NFC
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/118969
>From db963803f1a84b7deae31330e9c2f74df85a01cd Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Fri, 6 Dec 2024 13:09:23 +
Subject: [PATCH] [AArch64] Refactor implementation of FP8 types (NFC)
*
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/119031
>From db963803f1a84b7deae31330e9c2f74df85a01cd Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Fri, 6 Dec 2024 13:09:23 +
Subject: [PATCH 1/3] [AArch64] Refactor implementation of FP8 types (NFC
momchil-velikov wrote:
> Is `__mfp8` a floating type? `isFloatingType()` on it returns `false`, was
> that the case before as well?
It was the case before and it's intentional. That type is more like a union of
two floating-point types.
https://github.com/llvm/llvm-project/pull/123604
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momchil-velikov wrote:
/cherry-pick 7939ce6295e7fc0214cd307f97dfccc0cabde381
https://github.com/llvm/llvm-project/pull/124968
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https://github.com/llvm/llvm-project/pull/125051
Saves including 4 files, reduces the number of switch cases, less error prone
when adding new types,
at the "cost" of adding a` default:`.
>From 8719394b628da73a0f9ed7088d771f14fe238144 Mon Sep 17 00:00
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@@ -2808,6 +2812,7 @@ void MicrosoftCXXNameMangler::mangleType(const
BuiltinType *T, Qualifiers,
#define SVE_TYPE(Name, Id, SingletonId) \
case BuiltinType::Id:
+#define SVE_SCALAR_TYPE(Name, MangledName, Id, SingletonId, Bits)
momchil-velikov wrote:
> Wit
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@@ -529,6 +531,9 @@ llvm::Type *CodeGenTypes::ConvertType(QualType T) {
}
case BuiltinType::SveCount:
return llvm::TargetExtType::get(getLLVMContext(), "aarch64.svcount");
+case BuiltinType::MFloat8:
momchil-velikov wrote:
How else would yo
@@ -57,6 +57,11 @@
// - IsBF true for vector of brain float elements.
//===--===//
+#ifndef SVE_SCALAR_TYPE
+#define SVE_SCALAR_TYPE(Name, MangledName, Id, SingletonId, Bits) \
momchil-velik
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@@ -243,6 +243,7 @@ AArch64ABIInfo::convertFixedToScalableVectorType(const
VectorType *VT) const {
case BuiltinType::SChar:
case BuiltinType::UChar:
+case BuiltinType::MFloat8:
momchil-velikov wrote:
Intrinsics are not relevant here.
This is cove
@@ -761,8 +762,10 @@ bool AArch64ABIInfo::passAsPureScalableType(
getContext().getBuiltinVectorTypeInfo(cast(Ty));
assert(Info.NumVectors > 0 && Info.NumVectors <= 4 &&
"Expected 1, 2, 3 or 4 vectors!");
- auto VTy = llvm::ScalableVectorType::get(CGT.ConvertTy
@@ -529,6 +531,9 @@ llvm::Type *CodeGenTypes::ConvertType(QualType T) {
}
case BuiltinType::SveCount:
return llvm::TargetExtType::get(getLLVMContext(), "aarch64.svcount");
+case BuiltinType::MFloat8:
momchil-velikov wrote:
> What is the dif
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@@ -4374,15 +4379,18 @@ ASTContext::getBuiltinVectorTypeInfo(const BuiltinType
*Ty) const {
ElBits, NF)
\
case BuiltinType::Id:
\
return {BFloat16T
@@ -4374,15 +4379,18 @@ ASTContext::getBuiltinVectorTypeInfo(const BuiltinType
*Ty) const {
ElBits, NF)
\
case BuiltinType::Id:
\
return {BFloat16T
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/118126
>From 5bc5078af32cda3dbcf3ca8dd53b01996ad34ea1 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 25 Nov 2024 17:21:55 +
Subject: [PATCH 1/3] [AArch64] Implements FP8 SVE intrinsics for dot-pr
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/118125
>From 5bc5078af32cda3dbcf3ca8dd53b01996ad34ea1 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 25 Nov 2024 17:21:55 +
Subject: [PATCH 1/2] [AArch64] Implements FP8 SVE intrinsics for dot-pr
@@ -2468,4 +2468,30 @@ let SVETargetGuard = "sve2,fp8", SMETargetGuard =
"sme2,fp8" in {
// 8-bit floating-point convert to BFloat16/Float16 (top)
def SVF1CVTLT : SInst<"svcvtlt1_{d}[_mf8]_fpm", "d~>", "bh", MergeNone,
"aarch64_sve_fp8_cvtlt1", [VerifyRuntimeMode, SetsFPMR
@@ -10719,7 +10719,16 @@ Value *CodeGenFunction::EmitSVEDupX(Value *Scalar,
llvm::Type *Ty) {
cast(Ty)->getElementCount(), Scalar);
}
-Value *CodeGenFunction::EmitSVEDupX(Value* Scalar) {
+Value *CodeGenFunction::EmitSVEDupX(Value *Scalar) {
+ if (auto *Ty = Scalar->ge
@@ -10719,7 +10719,16 @@ Value *CodeGenFunction::EmitSVEDupX(Value *Scalar,
llvm::Type *Ty) {
cast(Ty)->getElementCount(), Scalar);
}
-Value *CodeGenFunction::EmitSVEDupX(Value* Scalar) {
+Value *CodeGenFunction::EmitSVEDupX(Value *Scalar) {
+ if (auto *Ty = Scalar->ge
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>From a83b190b25f01843922530d9e409cfb9c0a86c18 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Fri, 6 Dec 2024 13:09:23 +
Subject: [PATCH 1/4] [AArch64] Refactor implementation of FP8 types (NFC
momchil-velikov wrote:
- added the tests
- fixed calls to the wrong LLVM intrinsic
https://github.com/llvm/llvm-project/pull/119033
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>From 6f268d4a80a8994855c99679ce1c66c11be8e357 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 25 Nov 2024 09:47:41 +
Subject: [PATCH] [AArch64] Implement FP8 SVE Intrinsics for narrowing
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>From 359e611dc5a74d4e2dfdb19119eb8f83badb1f0b Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Thu, 21 Nov 2024 11:21:29 +
Subject: [PATCH 1/4] [AArch64] Implement FP8 SVE intrinsics for widenin
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/118123
>From 359e611dc5a74d4e2dfdb19119eb8f83badb1f0b Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Thu, 21 Nov 2024 11:21:29 +
Subject: [PATCH] [AArch64] Implement FP8 SVE intrinsics for widening
c
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/118124
>From 359e611dc5a74d4e2dfdb19119eb8f83badb1f0b Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Thu, 21 Nov 2024 11:21:29 +
Subject: [PATCH 1/2] [AArch64] Implement FP8 SVE intrinsics for widenin
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/118961
>From 7d4c0cded14845fe854157d550fafd4637bea14f Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Fri, 6 Dec 2024 10:47:43 +
Subject: [PATCH] Fix SVE tuples
---
clang/lib/CodeGen/Targets/AArch64.
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https://github.com/llvm/llvm-project/pull/119033
>From 1a9c550599b155fbfee3bdbdf0f43bf52dd14b11 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Fri, 6 Dec 2024 13:09:23 +
Subject: [PATCH 1/7] [AArch64] Refactor implementation of FP8 types (NFC
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/119031
>From 1a9c550599b155fbfee3bdbdf0f43bf52dd14b11 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Fri, 6 Dec 2024 13:09:23 +
Subject: [PATCH 1/3] [AArch64] Refactor implementation of FP8 types (NFC
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/118969
>From 1a9c550599b155fbfee3bdbdf0f43bf52dd14b11 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Fri, 6 Dec 2024 13:09:23 +
Subject: [PATCH] [AArch64] Refactor implementation of FP8 types (NFC)
*
https://github.com/momchil-velikov converted_to_draft
https://github.com/llvm/llvm-project/pull/120476
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@@ -0,0 +1,114 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc -mattr=+sve2,+fp8,+fp8fma < %s | FileCheck %s
+; RUN: llc -mattr=+sme,+fp8,+ssve-fp8fma --force-streaming < %s | FileCheck %s
+
+target triple = "aa
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/118126
>From 5bc5078af32cda3dbcf3ca8dd53b01996ad34ea1 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 25 Nov 2024 17:21:55 +
Subject: [PATCH 1/4] [AArch64] Implements FP8 SVE intrinsics for dot-pr
@@ -0,0 +1,114 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc -mattr=+sve2,+fp8,+fp8fma < %s | FileCheck %s
+; RUN: llc -mattr=+sme,+fp8,+ssve-fp8fma --force-streaming < %s | FileCheck %s
+
+target triple = "aa
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/118126
>From 5bc5078af32cda3dbcf3ca8dd53b01996ad34ea1 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 25 Nov 2024 17:21:55 +
Subject: [PATCH 1/5] [AArch64] Implements FP8 SVE intrinsics for dot-pr
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/118126
>From 15478424a10e531d42f197dae5e2083e8d183c23 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Tue, 26 Nov 2024 18:01:03 +
Subject: [PATCH 1/3] [AArch64] Implement FP8 SVE intrinsics for fused
https://github.com/momchil-velikov closed
https://github.com/llvm/llvm-project/pull/118126
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https://github.com/momchil-velikov closed
https://github.com/llvm/llvm-project/pull/118125
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https://github.com/momchil-velikov approved this pull request.
https://github.com/llvm/llvm-project/pull/120551
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https://github.com/momchil-velikov approved this pull request.
https://github.com/llvm/llvm-project/pull/120549
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momchil-velikov wrote:
Thanks!
https://github.com/llvm/llvm-project/pull/118961
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https://github.com/momchil-velikov approved this pull request.
LGTM, cheers!
https://github.com/llvm/llvm-project/pull/116959
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momchil-velikov wrote:
> Thanks! Does this work need to be based on #118957 and #118961?
I rebased it on `main`. It creates a little conflict with
https://github.com/llvm/llvm-project/pull/118961 but
not a big deal, easy to resolve.
https://github.com/llvm/llvm-project/pull/118969
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/118969
>From a83b190b25f01843922530d9e409cfb9c0a86c18 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Fri, 6 Dec 2024 13:09:23 +
Subject: [PATCH] [AArch64] Refactor implementation of FP8 types (NFC)
*
https://github.com/momchil-velikov created
https://github.com/llvm/llvm-project/pull/119033
TODO: proper commit message
>From a83b190b25f01843922530d9e409cfb9c0a86c18 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Fri, 6 Dec 2024 13:09:23 +
Subject: [PATCH 1/3] [AArch64] Refactor imp
https://github.com/momchil-velikov created
https://github.com/llvm/llvm-project/pull/119031
The Neon vector types for FP8 (`__MFloat8x8_t` and `__MFloat8x16_t`) are
implemented as builtin types and need a special case in
`__builtin_shufflevector`
which is needed for the upcoming implementation
momchil-velikov wrote:
> Hi, @momchil-velikov, Hi, @CarolineConcatto, it will be great if you help to
> review this patch as soon as possible! Thank you！
Patch is accepted, you don't need more approvals, go ahead and commit.
https://github.com/llvm/llvm-project/pull/118109
@@ -650,6 +655,8 @@ llvm::Type *CodeGenTypes::ConvertType(QualType T) {
// An ext_vector_type of Bool is really a vector of bits.
llvm::Type *IRElemTy = VT->isExtVectorBoolType()
? llvm::Type::getInt1Ty(getLLVMContext())
+
@@ -12153,8 +12166,15 @@ static QualType DecodeTypeFromStr(const char *&Str,
const ASTContext &Context,
RequiresICE, false);
assert(!RequiresICE && "Can't require vector ICE");
-// TODO: No way to make AltiVec vectors in bu
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