@@ -148,10 +151,10 @@ void test_svpmov_lane(){
svuint64_t zn_u64;
svbool_t pn;
- svpmov_lane_u8(zn_u8, -1); // expected-error {{argument value -1 is outside
the valid range [0, 0]}}
- svpmov_lane_u16(zn_u16, -1); // expected-error {{argument value -1 is
outside the val
@@ -1,12 +1,20 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S
-O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -t
https://github.com/momchil-velikov created
https://github.com/llvm/llvm-project/pull/75596
According to the latest update of the ISA
https://developer.arm.com/documentation/ddi0602/2023-09/?lang=en all of the
affected instruction encodings now require
(FEAT_SVE2 or FEAT_SME2) and FEAT_SVE_
@@ -1702,6 +1705,62 @@ void SVEEmitter::createSMERangeChecks(raw_ostream &OS) {
OS << "#endif\n\n";
}
+void SVEEmitter::createStreamingAttrs(raw_ostream &OS, ACLEKind Kind) {
+ std::vector RV = Records.getAllDerivedDefinitions("Inst");
+ SmallVector, 128> Defs;
+ for (aut
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/75117
>From e11897d680dbb892aa645a6fc7f63f91fde3bd7c Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 11 Dec 2023 23:25:07 +
Subject: [PATCH 1/2] [Clang][SVE2.1] Add floating-point variants of
`sv
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/75200
>From bb881371fb036819a1d6489a9779e2c5ac7e7d3c Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Tue, 12 Dec 2023 15:08:33 +
Subject: [PATCH 1/4] [Clang][SVE2.1] Make the part of the name optional
https://github.com/momchil-velikov closed
https://github.com/llvm/llvm-project/pull/75107
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>From 979b240d2a084eb87db43d3fabfffa8d3351d294 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 11 Dec 2023 23:25:07 +
Subject: [PATCH 1/2] [Clang][SVE2.1] Add floating-point variants of
`sv
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/75200
>From d97312680eff280210f588ef22416f845d31d2ef Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Tue, 12 Dec 2023 15:08:33 +
Subject: [PATCH 1/4] [Clang][SVE2.1] Make the part of the name optional
https://github.com/momchil-velikov closed
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>From fc5c82e61efef3f1cd2f6606b12c358637a687f5 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Fri, 15 Dec 2023 12:18:53 +
Subject: [PATCH 1/2] [AArch64] Update target feature requirements of SVE
@@ -2066,7 +2066,7 @@ let TargetGuard = "sve2p1|sme2" in {
def SVPFALSE_COUNT_ALIAS : SInst<"svpfalse_c", "}v", "", MergeNone, "",
[IsOverloadNone, IsStreamingCompatible]>;
}
-let TargetGuard = "sve2p1,b16b16" in {
+let TargetGuard = "(sve2|sme2),b16b16" in {
--
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/75596
>From 04a03eae3fcbdd57257ce3867615ec6be9d84e53 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Fri, 15 Dec 2023 12:18:53 +
Subject: [PATCH 1/2] [AArch64] Update target feature requirements of SVE
momchil-velikov wrote:
Rebased the clear the test run.
https://github.com/llvm/llvm-project/pull/75596
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@@ -2086,7 +2086,7 @@ let TargetGuard = "sve2p1|sme2" in {
def SVCNTP_COUNT : SInst<"svcntp_{d}", "n}i", "QcQsQiQl", MergeNone,
"aarch64_sve_cntp_{d}", [IsOverloadNone, IsStreamingCompatible], [ImmCheck<1,
ImmCheck2_4_Mul2>]>;
}
-let TargetGuard = "sve2p1,b16b16" in {
+let
@@ -2086,7 +2086,7 @@ let TargetGuard = "sve2p1|sme2" in {
def SVCNTP_COUNT : SInst<"svcntp_{d}", "n}i", "QcQsQiQl", MergeNone,
"aarch64_sve_cntp_{d}", [IsOverloadNone, IsStreamingCompatible], [ImmCheck<1,
ImmCheck2_4_Mul2>]>;
}
-let TargetGuard = "sve2p1,b16b16" in {
+let
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https://github.com/llvm/llvm-project/pull/68993
>From 553f647e3f8460e376b8a09233b23a0bd6b12ead Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Wed, 11 Oct 2023 17:22:51 +0100
Subject: [PATCH 1/2] [clang][AArch64] Pass down stack clash protection o
@@ -1757,46 +1826,55 @@ void AArch64FrameLowering::emitPrologue(MachineFunction
&MF,
}
}
- StackOffset AllocateBefore = SVEStackSize, AllocateAfter = {};
+ StackOffset SVECalleeSavedSize = {}, SVELocalsSize = SVEStackSize;
MachineBasicBlock::iterator CalleeSavesBeg
@@ -0,0 +1,722 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple aarch64-none-eabi < %s -verify-machineinstrs | FileCheck %s
+; RUN: llc -mtriple aarch64-none-eabi < %s -verify-machineinstrs -global-isel
-global-isel-abort=2 |
@@ -9461,6 +9462,94 @@ bool AArch64InstrInfo::isReallyTriviallyReMaterializable(
return TargetInstrInfo::isReallyTriviallyReMaterializable(MI);
}
+MachineBasicBlock::iterator
+AArch64InstrInfo::probedStackAlloc(MachineBasicBlock::iterator MBBI,
momchil-velik
@@ -861,6 +861,12 @@ def AArch64stilp : SDNode<"AArch64ISD::STILP",
SDT_AArch64stilp, [SDNPHasChain,
def AArch64stnp : SDNode<"AArch64ISD::STNP", SDT_AArch64stnp, [SDNPHasChain,
SDNPMayStore, SDNPMemOperand]>;
def AArch64tbl : SDNode<"AArch64ISD::TBL", SDT_AArch64TBL>;
+
+de
@@ -0,0 +1,363 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple aarch64-none-eabi < %s -verify-machineinstrs | FileCheck %s
+
+; Dynamically-sized allocation, needs a loop which can handle any size at
+; runtime. The final iter
@@ -1076,6 +1076,16 @@ void CodeGenModule::Release() {
"sign-return-address-with-bkey", 1);
}
+ if (Arch == llvm::Triple::aarch64 || Arch == llvm::Triple::aarch64_be) {
momchil-velikov wrote:
Done, we now emit both
https://
@@ -196,11 +196,14 @@ llvm::MDNode *CodeGenTBAA::getTypeInfoHelper(const Type
*Ty) {
// Enum types are distinct types. In C++ they have "underlying types",
// however they aren't related for TBAA.
if (const EnumType *ETy = dyn_cast(Ty)) {
+if (!Features.CPlusPlus)
+
momchil-velikov wrote:
> Do the call frame changes here affect Windows? (I guess that would indicate a
> latent bug in our Windows ABI support...)
TBH, I have not tested on Windows. However, by construction, I've hopefully
made sure the Windows and non-Windows are isolated and separate - eithe
momchil-velikov wrote:
Ping?
https://github.com/llvm/llvm-project/pull/70565
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>From 66a84fffb5d1b5c34eea9ecdb83a88afb0b627ff Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Sat, 28 Oct 2023 15:01:36 +0100
Subject: [PATCH 1/4] [Verifier] Check function attributes related to bra
https://github.com/momchil-velikov closed
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@@ -81,6 +81,15 @@ static bool DecodeAArch64Features(const Driver &D, StringRef
text,
else
return false;
+// +jsconv and +complxnum implies +neon and +fp-armv8
momchil-velikov wrote:
According to the latest Arm ARM
(https://developer.arm.com/d
https://github.com/momchil-velikov approved this pull request.
https://github.com/llvm/llvm-project/pull/76844
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Author: Momchil Velikov
Date: 2022-02-14T15:59:26Z
New Revision: a31d00ddceb057291ef3a094c57ae36975e804fe
URL:
https://github.com/llvm/llvm-project/commit/a31d00ddceb057291ef3a094c57ae36975e804fe
DIFF:
https://github.com/llvm/llvm-project/commit/a31d00ddceb057291ef3a094c57ae36975e804fe.diff
LO
@@ -10007,6 +10007,16 @@ multiclass sve2p1_dupq {
bits<1> index;
let Inst{20} = index;
}
+
+ def : SVE_2_Op_Imm_Pat(NAME # _B)>;
momchil-velikov wrote:
Change them to `_timm`.
https://github.com/llvm/llvm-project/pull/83260
@@ -1,336 +1,813 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: aarch64-registered-target
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve
-target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm
@@ -1,336 +1,813 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: aarch64-registered-target
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve
-target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm
momchil-velikov wrote:
Ping?
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Ping?
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@@ -85,17 +90,32 @@ static bool isPrologueCFIInstruction(const MachineInstr
&MI) {
MI.getFlag(MachineInstr::FrameSetup);
}
-static bool containsPrologue(const MachineBasicBlock &MBB) {
- return llvm::any_of(MBB.instrs(), isPrologueCFIInstruction);
-}
-
static bool
@@ -1,25 +1,33 @@
// Check the correct function attributes are generated
-// RUN: %clang_cc1 -triple x86_64-linux -O0 -S -emit-llvm -o- %s
-fstack-clash-protection | FileCheck %s
-// RUN: %clang_cc1 -triple s390x-linux-gnu -O0 -S -emit-llvm -o- %s
-fstack-clash-protection | Fil
https://github.com/momchil-velikov edited
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momchil-velikov wrote:
> I think it is fine to point also the PR in the acle in the commit message:
> https://github.com/ARM-software/acle/pull/275/files
Done.
https://github.com/llvm/llvm-project/pull/69598
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@@ -263,17 +267,11 @@ class SVEEmitter {
// which is inconvenient to specify in the arm_sve.td file or
// generate in CGBuiltin.cpp.
struct ReinterpretTypeInfo {
+SVEType BaseType;
const char *Suffix;
-const char *Type;
-const char *BuiltinType;
};
-
momchil-velikov wrote:
> I haven't been able to produce a minimal, sharable example as of yet, but I'm
> encountering a runtime error associated with an inlined function where stack
> probing is active. The error manifests as a null pointer dereference,
> originating from a stack value that i
momchil-velikov wrote:
> Apologies for still not being able to create a reproducible example I can
> share but what I am seeing is the stack probe write overwriting the value at
> the tip of the stack when I step debug execution:
Can you spot a place where the probe instruction is *not* immedi
@@ -64,26 +65,29 @@ class ImmCheck {
};
class SVEType {
- TypeSpec TS;
bool Float, Signed, Immediate, Void, Constant, Pointer, BFloat;
bool DefaultType, IsScalable, Predicate, PredicatePattern, PrefetchOp,
Svcount;
unsigned Bitwidth, ElementBitwidth, NumVector
https://github.com/momchil-velikov edited
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@@ -383,6 +381,20 @@ class SVEEmitter {
SmallVectorImpl> &Out);
};
+const std::array SVEEmitter::Reinterprets
=
+{{{SVEType("c"), "s8"},
momchil-velikov wrote:
Ok, I'll do that.
https://github.com/llvm/llvm-project/pull/69598
@@ -954,13 +967,13 @@ std::string Intrinsic::replaceTemplatedArgs(std::string
Name, TypeSpec TS,
default:
llvm_unreachable("Unknown predication specifier");
case 'd':
- T = SVEType(TS, 'd');
+ T = SVEType(TS, 'd', 1);
momchil-velikov wr
@@ -64,26 +65,29 @@ class ImmCheck {
};
class SVEType {
- TypeSpec TS;
bool Float, Signed, Immediate, Void, Constant, Pointer, BFloat;
bool DefaultType, IsScalable, Predicate, PredicatePattern, PrefetchOp,
Svcount;
unsigned Bitwidth, ElementBitwidth, NumVector
@@ -383,6 +381,20 @@ class SVEEmitter {
SmallVectorImpl> &Out);
};
+const std::array SVEEmitter::Reinterprets
=
+{{{SVEType("c"), "s8"},
momchil-velikov wrote:
Done
https://github.com/llvm/llvm-project/pull/69598
_
Author: chill
Date: Thu Aug 10 08:43:06 2017
New Revision: 310616
URL: http://llvm.org/viewvc/llvm-project?rev=310616&view=rev
Log:
Place implictly declared functions at block scope
Such implicitly declared functions behave as if the enclosing block
contained the declaration extern int name() (C9
Author: Momchil Velikov
Date: 2020-01-09T14:03:25Z
New Revision: 173b711e83d7b61a46f55eb44f03ea98f69a1dd6
URL:
https://github.com/llvm/llvm-project/commit/173b711e83d7b61a46f55eb44f03ea98f69a1dd6
DIFF:
https://github.com/llvm/llvm-project/commit/173b711e83d7b61a46f55eb44f03ea98f69a1dd6.diff
LO
Author: Momchil Velikov
Date: 2020-09-25T11:47:14+01:00
New Revision: a88c722e687e6780dcd6a58718350dc76fcc4cc9
URL:
https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9
DIFF:
https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9.dif
Author: Momchil Velikov
Date: 2021-05-24T22:04:15+01:00
New Revision: 13dd65b3a1a3ac049b5f3a9712059f7c61649bea
URL:
https://github.com/llvm/llvm-project/commit/13dd65b3a1a3ac049b5f3a9712059f7c61649bea
DIFF:
https://github.com/llvm/llvm-project/commit/13dd65b3a1a3ac049b5f3a9712059f7c61649bea.dif
Author: Momchil Velikov
Date: 2021-05-25T15:54:40+01:00
New Revision: 21aa107eb79f8ddc5e7ca4e8f3476338dfa90049
URL:
https://github.com/llvm/llvm-project/commit/21aa107eb79f8ddc5e7ca4e8f3476338dfa90049
DIFF:
https://github.com/llvm/llvm-project/commit/21aa107eb79f8ddc5e7ca4e8f3476338dfa90049.dif
https://github.com/momchil-velikov created
https://github.com/llvm/llvm-project/pull/68993
None
>From 870650ae6e2c5b7f34c4d0b1572c5f6a88b6e9b6 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 2 Oct 2023 14:46:27 +0100
Subject: [PATCH 1/2] [CFIFixup] Allow function prologues to span mo
@@ -1076,6 +1076,16 @@ void CodeGenModule::Release() {
"sign-return-address-with-bkey", 1);
}
+ if (Arch == llvm::Triple::aarch64 || Arch == llvm::Triple::aarch64_be) {
momchil-velikov wrote:
Stack probing needs to be enable
@@ -2287,7 +2297,7 @@ void
CodeGenModule::SetLLVMFunctionAttributesForDefinition(const Decl *D,
if ((!D || !D->hasAttr()) && CodeGenOpts.UnwindTables)
B.addUWTableAttr(llvm::UWTableKind(CodeGenOpts.UnwindTables));
- if (CodeGenOpts.StackClashProtector)
+ if (CodeGenOp
Author: Momchil Velikov
Date: 2020-03-23T11:03:13Z
New Revision: 6081ccf4a3b6289717c8ae558ac210c36ddcbfbe
URL:
https://github.com/llvm/llvm-project/commit/6081ccf4a3b6289717c8ae558ac210c36ddcbfbe
DIFF:
https://github.com/llvm/llvm-project/commit/6081ccf4a3b6289717c8ae558ac210c36ddcbfbe.diff
LO
Author: Momchil Velikov
Date: 2020-03-24T10:21:26Z
New Revision: 080d046c91d26bd3b0afba817cf5c2f99d1288ff
URL:
https://github.com/llvm/llvm-project/commit/080d046c91d26bd3b0afba817cf5c2f99d1288ff
DIFF:
https://github.com/llvm/llvm-project/commit/080d046c91d26bd3b0afba817cf5c2f99d1288ff.diff
LO
From: Russell Gallop
> The new case that you've added to save-temps.c doesn't work if you only build
> with
> DLLVM_TARGETS_TO_BUILD=X86 (i.e. not building ARM). Please could you take a
> look?
Yes, I've been looking into it. I may revert that test alone, until I figure
out how to fix it. http
Author: Momchil Velikov
Date: 2019-11-15T15:40:46Z
New Revision: aa6d48fa70eb5d1769ea09ac0a2c4d956deeb06d
URL:
https://github.com/llvm/llvm-project/commit/aa6d48fa70eb5d1769ea09ac0a2c4d956deeb06d
DIFF:
https://github.com/llvm/llvm-project/commit/aa6d48fa70eb5d1769ea09ac0a2c4d956deeb06d.diff
LO
Author: Momchil Velikov
Date: 2019-12-12T15:01:14Z
New Revision: 600d123c6ff16180a20ebb9b55476257bf69513a
URL:
https://github.com/llvm/llvm-project/commit/600d123c6ff16180a20ebb9b55476257bf69513a
DIFF:
https://github.com/llvm/llvm-project/commit/600d123c6ff16180a20ebb9b55476257bf69513a.diff
LO
Author: Momchil Velikov
Date: 2020-02-05T16:07:51Z
New Revision: 3627c91ead934486fdb3986b911482a78f101309
URL:
https://github.com/llvm/llvm-project/commit/3627c91ead934486fdb3986b911482a78f101309
DIFF:
https://github.com/llvm/llvm-project/commit/3627c91ead934486fdb3986b911482a78f101309.diff
LO
Author: Momchil Velikov
Date: 2020-02-11T12:03:41Z
New Revision: da3f2b414ace1f24054ae9255f811b653d9cff99
URL:
https://github.com/llvm/llvm-project/commit/da3f2b414ace1f24054ae9255f811b653d9cff99
DIFF:
https://github.com/llvm/llvm-project/commit/da3f2b414ace1f24054ae9255f811b653d9cff99.diff
LO
Author: Momchil Velikov
Date: 2020-01-29T10:39:01Z
New Revision: ac215354607450191b9d63be72c00efe36b53a1c
URL:
https://github.com/llvm/llvm-project/commit/ac215354607450191b9d63be72c00efe36b53a1c
DIFF:
https://github.com/llvm/llvm-project/commit/ac215354607450191b9d63be72c00efe36b53a1c.diff
LO
Author: chill
Date: Mon Jul 24 02:19:32 2017
New Revision: 308871
URL: http://llvm.org/viewvc/llvm-project?rev=308871&view=rev
Log:
[libunwind] Handle .ARM.exidx tables without sentinel last entry
UnwindCursor::getInfoFromEHABISection assumes the last
entry in the index table never corresponds to
@@ -545,6 +545,25 @@ let TargetPrefix = "aarch64", IntrProperties = [IntrNoMem]
in {
def int_aarch64_neon_vcmla_rot270 : AdvSIMD_3VectorArg_Intrinsic;
}
+let TargetPrefix = "aarch64" in {
+def int_aarch64_neon_vluti2_lane : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
---
https://github.com/momchil-velikov edited
https://github.com/llvm/llvm-project/pull/96883
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momchil-velikov wrote:
Ping?
https://github.com/llvm/llvm-project/pull/99041
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momchil-velikov wrote:
Rebased.
https://github.com/llvm/llvm-project/pull/99042
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https://github.com/momchil-velikov closed
https://github.com/llvm/llvm-project/pull/99042
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https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/99063
>From f85636d61ecd16fdc88317c53ddd00558e37f99a Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Tue, 16 Jul 2024 16:49:04 +0100
Subject: [PATCH] [AArch64] Implement intrinsics for SME2 FAMIN/FAMAX
Th
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/99041
>From 886c48dd7efa227f8605bfafef4204cefbb75d6e Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 15 Jul 2024 17:50:43 +0100
Subject: [PATCH 1/3] [AArch64] Implement NEON vamin/vamax intrinsics
Th
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/99041
>From 886c48dd7efa227f8605bfafef4204cefbb75d6e Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 15 Jul 2024 17:50:43 +0100
Subject: [PATCH 1/4] [AArch64] Implement NEON vamin/vamax intrinsics
Th
@@ -2115,3 +2115,8 @@ let ArchGuard = "defined(__aarch64__)", TargetGuard =
"lut" in {
def VLUTI4_BF_X2_Q : SInst<"vluti4_laneq_x2", ".2(;
}
}
+
+let ArchGuard = "defined(__aarch64__)", TargetGuard = "faminmax" in {
momchil-velikov wrote:
Done
https:
@@ -2582,6 +2582,60 @@ void NeonEmitter::runVectorTypes(raw_ostream &OS) {
OS << "typedef double float64_t;\n";
OS << "#endif\n\n";
+ OS << R"(
+typedef uint64_t fpm_t;
+
+enum __ARM_FPM_FORMAT { __ARM_FPM_E5M2, __ARM_FPM_E4M3 };
+
+enum __ARM_FPM_OVERFLOW { __ARM_FPM_INF
@@ -0,0 +1,165 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 5
+
+// RUN: %clang_cc1 -O2 -triple aarch64 -emit-llvm -x c -DUSE_NEON_H %s -o -
| FileCheck %s
+// RUN: %clang_cc1 -O2 -triple aarch64 -emit-llvm -x c -DUSE
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/99041
>From 0cca71a770750e34474d7734c8f803fb31feacee Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 15 Jul 2024 17:50:43 +0100
Subject: [PATCH 1/4] [AArch64] Implement NEON vamin/vamax intrinsics
Th
https://github.com/momchil-velikov closed
https://github.com/llvm/llvm-project/pull/99041
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https://github.com/momchil-velikov created
https://github.com/llvm/llvm-project/pull/88105
According to the specification in
https://github.com/ARM-software/acle/pull/309 this adds the intrinsics
void svmopa_za16[_f16]_m(uint64_t tile, svbool_t pn, svbool_t pm,
momchil-velikov wrote:
> I noticed that file names and file location are using sme2 as prefix.
> Shouldn't we use sme2p1 prefix for this intrinsic ?
None of instructions seem to require `FEAT_SME2p1`:
https://developer.arm.com/documentation/ddi0602/2024-03/SME-Instructions/BFMOPA--non-widening-
@@ -2148,6 +2148,11 @@ let TargetGuard = "sme2" in {
def SVSCLAMP_X4 : SInst<"svclamp[_single_{d}_x4]", "44dd", "csil",
MergeNone, "aarch64_sve_sclamp_single_x4", [IsStreaming], []>;
def SVUCLAMP_X4 : SInst<"svclamp[_single_{d}_x4]", "44dd", "UcUsUiUl",
MergeNon
https://github.com/momchil-velikov created
https://github.com/llvm/llvm-project/pull/88266
According to the specification in
https://github.com/ARM-software/acle/pull/309 this adds the intrinsics
void_svadd_za16_vg1x2_f16(uint32_t slice, svfloat16x2_t zn) __arm_streaming
__arm_inout("za");
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/88105
>From 2b0befb9078f8c9116ad52be937c8722045708ef Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Tue, 9 Apr 2024 10:52:41 +0100
Subject: [PATCH] [AArch64] Add intrinsics for non-widening FMOPA/FMOPS
A
@@ -674,3 +674,27 @@ let TargetGuard = "sme2" in {
def SVLUTI2_LANE_ZT_X2 : Inst<"svluti2_lane_zt_{d}_x2", "2.di[i",
"cUcsUsiUibhf", MergeNone, "aarch64_sme_luti2_lane_zt_x2", [IsStreaming,
IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_7>]>;
def SVLUTI4_LANE_Z
@@ -674,3 +674,27 @@ let TargetGuard = "sme2" in {
def SVLUTI2_LANE_ZT_X2 : Inst<"svluti2_lane_zt_{d}_x2", "2.di[i",
"cUcsUsiUibhf", MergeNone, "aarch64_sme_luti2_lane_zt_x2", [IsStreaming,
IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_7>]>;
def SVLUTI4_LANE_Z
@@ -815,8 +815,8 @@ defm FMLS_VG4_M4Z2Z_H :
sme2_dot_mla_add_sub_array_vg4_multi<"fmls", 0b0100011,
defm FCVT_2ZZ_H : sme2p1_fp_cvt_vector_vg2_single<"fcvt", 0b0>;
defm FCVTL_2ZZ_H : sme2p1_fp_cvt_vector_vg2_single<"fcvtl", 0b1>;
-defm FMOPA_MPPZZ_H : sme2p1_fmop_tile_fp16<"
@@ -674,3 +674,27 @@ let TargetGuard = "sme2" in {
def SVLUTI2_LANE_ZT_X2 : Inst<"svluti2_lane_zt_{d}_x2", "2.di[i",
"cUcsUsiUibhf", MergeNone, "aarch64_sme_luti2_lane_zt_x2", [IsStreaming,
IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_7>]>;
def SVLUTI4_LANE_Z
@@ -118,6 +124,37 @@ llvm::Type *CodeGenTypes::ConvertTypeForMem(QualType T,
bool ForBitField) {
return R;
}
+bool CodeGenTypes::LLVMTypeLayoutMatchesAST(QualType ASTTy,
+llvm::Type *LLVMTy) {
+ CharUnits ASTSize = Context.getTyp
@@ -118,6 +124,37 @@ llvm::Type *CodeGenTypes::ConvertTypeForMem(QualType T,
bool ForBitField) {
return R;
}
+bool CodeGenTypes::LLVMTypeLayoutMatchesAST(QualType ASTTy,
+llvm::Type *LLVMTy) {
+ CharUnits ASTSize = Context.getTyp
@@ -8084,29 +8084,6 @@ static void HandleNeonVectorTypeAttr(QualType &CurType,
const ParsedAttr &Attr,
AuxTI && (AuxTI->getTriple().isAArch64() ||
AuxTI->getTriple().isARM());
}
- // Target must have NEON (or MVE, whose vectors are similar enough
- // not to need
momchil-velikov wrote:
> > This patch removes FEAT_FPMR from list of available of architecture
> > features, instead enabling FMPR register by default.
>
> Can you expand a little bit on the reasoning? It doesn't seem all that
> problematic but is still eyebrow-raising.
The overall idea is th
@@ -221,6 +221,16 @@ bool AArch64TargetInfo::validateTarget(DiagnosticsEngine
&Diags) const {
return true;
}
+unsigned AArch64TargetInfo::getBitIntLegalWidth(unsigned Width) const {
momchil-velikov wrote:
This function is likely unnecessary (also it's inco
@@ -2021,6 +2028,12 @@ llvm::Value *CodeGenFunction::EmitToMemory(llvm::Value
*Value, QualType Ty) {
assert(Value->getType()->isIntegerTy(getContext().getTypeSize(Ty)) &&
"wrong value rep of bool");
}
+ if (auto *BitIntTy = Ty->getAs()) {
+if (CGM.getTarg
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