[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)

https://github.com/mshockwave updated https://github.com/llvm/llvm-project/pull/117368 >From 599370a06008092f6aa883bf11600d0b66707bc0 Mon Sep 17 00:00:00 2001 From: Min-Yih Hsu Date: Wed, 20 Nov 2024 14:37:57 -0800 Subject: [PATCH 1/8] [XRay][RISCV] RISCV support for XRay Add RISC-V support fo

[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)

@@ -0,0 +1,266 @@ +//===-- xray_riscv.cpp *- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apach

[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)

@@ -0,0 +1,266 @@ +//===-- xray_riscv.cpp *- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apach

[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)

@@ -1575,6 +1575,26 @@ unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const { // No patch bytes means at most a PseudoCall is emitted return std::max(NumBytes, 8U); } + case TargetOpcode::PATCHABLE_FUNCTION_ENTER: + case TargetOpcode::PATCHABLE

[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)

https://github.com/mshockwave closed https://github.com/llvm/llvm-project/pull/117368 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add scheduling model for mips p8700 CPU (PR #119885)

@@ -0,0 +1,290 @@ +//===-- RISCVSchedMIPSP8700.td - MIPS RISC-V Processor -*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [llvm] [RISCV] Add scheduling model for mips p8700 CPU (PR #119885)

@@ -0,0 +1,290 @@ +//===-- RISCVSchedMIPSP8700.td - MIPS RISC-V Processor -*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [llvm] [RISCV] Add scheduling model for mips p8700 CPU (PR #119885)

@@ -0,0 +1,290 @@ +//===-- RISCVSchedMIPSP8700.td - MIPS RISC-V Processor -*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [llvm] [RISCV] Add scheduling model for mips p8700 CPU (PR #119885)

@@ -0,0 +1,290 @@ +//===-- RISCVSchedMIPSP8700.td - MIPS RISC-V Processor -*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [llvm] [RISCV] Add scheduling model for mips p8700 CPU (PR #119885)

@@ -0,0 +1,290 @@ +//===-- RISCVSchedMIPSP8700.td - MIPS RISC-V Processor -*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [llvm] [RISCV] Add scheduling model for mips p8700 CPU (PR #119885)

@@ -0,0 +1,290 @@ +//===-- RISCVSchedMIPSP8700.td - MIPS RISC-V Processor -*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)

https://github.com/mshockwave created https://github.com/llvm/llvm-project/pull/117368 Add RISC-V support for XRay. The RV64 implementation has been tested in both QEMU and in our production environment. Currently this requires D and C extensions, but since both RV64GC and RVA22/RVA23 are bec

[clang] [compiler-rt] [llvm] [XRay][RISCV] RISCV support for XRay (PR #117368)

https://github.com/mshockwave edited https://github.com/llvm/llvm-project/pull/117368 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [compiler-rt] [llvm] [XRay] Add `-fxray-default-options` to pass build-time defined XRay options (PR #116878)

https://github.com/mshockwave updated https://github.com/llvm/llvm-project/pull/116878 >From 95ee4bd09aa48d4f0c2c4f5fc1e81e20cd57c7e2 Mon Sep 17 00:00:00 2001 From: Min-Yih Hsu Date: Mon, 11 Nov 2024 11:40:43 -0800 Subject: [PATCH 1/2] [XRay] Add `-fxray-default-options` to pass build-time def

[clang] [llvm] [mlir] [TableGen] Only store direct superclasses in Record (PR #123072)

https://github.com/mshockwave approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/123072 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [mlir] [TableGen] Only store direct superclasses in Record (PR #123072)

@@ -1630,9 +1630,9 @@ class Record { SmallVector Assertions; SmallVector Dumps; - // All superclasses in the inheritance forest in post-order (yes, it + // Direct superclasses, which are roots of the inheritance forest (yes, it // must be a forest; diamond-shaped inhe

[clang] [llvm] [mlir] [TableGen] Only store direct superclasses in Record (PR #123072)

@@ -1718,15 +1719,30 @@ class Record { ArrayRef getAssertions() const { return Assertions; } ArrayRef getDumps() const { return Dumps; } - ArrayRef> getSuperClasses() const { -return SuperClasses; + /// Append all superclasses in post-order to \p Classes. + void get

[clang] [llvm] [mlir] [TableGen] Only store direct superclasses in Record (PR #123072)

@@ -3415,10 +3419,11 @@ namespace { AttrClass *findSuperClass(const Record *R) const { // TableGen flattens the superclass list, so we just need to walk it // in reverse. - auto SuperClasses = R->getSuperClasses(); - for (signed i = 0, e = SuperClasses

[clang] [llvm] [RISCV] Add a generic OOO CPU (PR #120712)

@@ -0,0 +1,601 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=riscv64 -mattr=+rva23u64,+zabha -mcpu=generic-ooo --all-stats -iterations=1 < %s | FileCheck %s mshockwave wrote: nit: `--all-stats` shows

[clang] [llvm] [RISCV] Add a generic OOO CPU (PR #120712)

@@ -0,0 +1,494 @@ +//===-- RISCVSchedGenericOOO.td - Generic O3 Processor -*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [NFC][clang] Remove superfluous header files after refactor in #132252 (PR #132495)

mshockwave wrote: > If only `CGBuiltin.cpp` and `ARM.cpp` is touched/updated, I see a large > difference This. IMHO I think quality-of-life improvements on incremental build -- especially for LLVM developers -- is already a big thing that can justify this patch by itself. Regarding the margi

[clang] [llvm] [MIPS] Add FeatureMSA to i6400 and i6500 cores (PR #134985)

@@ -0,0 +1,9 @@ +// Check target CPUs are correctly passed. + +// RUN: %clang --target=mips64 -### -c %s 2>&1 -mcpu=i6400 -mmsa | FileCheck -check-prefix=MCPU-I6400 %s +// MCPU-I6400: "-target-cpu" "i6400" mshockwave wrote: usually we will check all the features

[clang] [llvm] [RISCV] Add processor definition for XiangShan-KunMingHu-V2R2 (PR #123193)

https://github.com/mshockwave approved this pull request. https://github.com/llvm/llvm-project/pull/123193 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Andes XAndesperf (Andes Performance) extension. (PR #135110)

@@ -0,0 +1,358 @@ +//===-- RISCVInstrInfoXAndes.td *- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [llvm] [RISCV] Add processor definition for SiFive P870 (PR #137725)

mshockwave wrote: > LLVM Buildbot has detected a new failure on builder `arc-builder` running on > `arc-worker` while building `clang,llvm` at step 6 > "test-build-unified-tree-check-all". > > Full details are available at: > https://lab.llvm.org/buildbot/#/builders/3/builds/15497 > > Here i

[clang] [llvm] [MIPS] Add FeatureMSA to i6400 and i6500 cores (PR #134985)

@@ -0,0 +1,724 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=mips64 -mcpu=i6500 < %s | FileCheck %s --check-prefixes=ALL +; RUN: llc -mtriple=mips64 -mcpu=i6400 < %s | FileCheck %s --check-prefixes=ALL mshoc

[clang] [llvm] [MIPS] Add FeatureMSA to i6400 and i6500 cores (PR #134985)

https://github.com/mshockwave commented: Sorry I missed the update. I only have some minor comments https://github.com/llvm/llvm-project/pull/134985 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo

[clang] [llvm] [MIPS] Add FeatureMSA to i6400 and i6500 cores (PR #134985)

https://github.com/mshockwave edited https://github.com/llvm/llvm-project/pull/134985 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [MIPS] Add FeatureMSA to i6400 and i6500 cores (PR #134985)

mshockwave wrote: I just noticed there is already `test/CodeGen/Mips/msa/arithmetic.ll` (which this file is probably based on), could add additional `RUN` lines to that file instead, in order to reuse it? https://github.com/llvm/llvm-project/pull/134985 _

[clang] [llvm] [RISCV] Add processor definition for SiFive P870 (PR #137725)

https://github.com/mshockwave closed https://github.com/llvm/llvm-project/pull/137725 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add processor definition for SiFive P870 (PR #137725)

@@ -365,6 +365,32 @@ def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", SiFiveP600Model, TuneVXRMPipelineFlush, TunePostRAScheduler]>; +def SIFIVE_P870 : RISCVProcessorModel<"sifive-p870", NoSched

[clang] [llvm] [RISCV] Remove duplicate extensions from tt-ascalon-d8 CPU (PR #137865)

https://github.com/mshockwave created https://github.com/llvm/llvm-project/pull/137865 Sscofpmf is already in RVA23S64 and Zicsr is in RVA20U64. I also added a test to check Sscofpmf. This is effectively an NFC. --- This is found by #137864 >From 3ac537e4fe391464870254d0a9c81fe9f58c195a

[clang] [llvm] [RISCV] Add processor definition for SiFive P870 (PR #137725)

https://github.com/mshockwave updated https://github.com/llvm/llvm-project/pull/137725 >From c8584c12408bcf8739558b3d9e0c2190f1d95bea Mon Sep 17 00:00:00 2001 From: Min-Yih Hsu Date: Mon, 28 Apr 2025 14:12:13 -0700 Subject: [PATCH 1/2] [RISCV] Add processor definition for SiFive P870 --- .../

[clang] [llvm] [RISCV] Add processor definition for SiFive P870 (PR #137725)

@@ -365,6 +365,32 @@ def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", SiFiveP600Model, TuneVXRMPipelineFlush, TunePostRAScheduler]>; +def SIFIVE_P870 : RISCVProcessorModel<"sifive-p870", NoSched

[clang] [llvm] [RISCV] Remove duplicate extensions from tt-ascalon-d8 CPU (PR #137865)

https://github.com/mshockwave edited https://github.com/llvm/llvm-project/pull/137865 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV][NFC] Remove duplicate extensions from tt-ascalon-d8 CPU (PR #137865)

https://github.com/mshockwave edited https://github.com/llvm/llvm-project/pull/137865 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV][NFC] Remove duplicate extensions from tt-ascalon-d8 CPU (PR #137865)

mshockwave wrote: > If the `"-target-feature" "+sscofpmf"` was already present in the test > output, just not looked for, then I think you should just mark this as > `[NFC]`. Agree. It's updated now. https://github.com/llvm/llvm-project/pull/137865

[clang] [llvm] [RISCV][NFC] Remove duplicate extensions from tt-ascalon-d8 CPU (PR #137865)

https://github.com/mshockwave closed https://github.com/llvm/llvm-project/pull/137865 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [LLVM][SROA] Teach SROA how to "bitcast" between fixed and scalable vectors. (PR #130973)

mshockwave wrote: > @pawosm-arm - I've removed the reviewers because it is not quite ready yet. I > need to investigate the potential regressions shown by the RISCV tests. you can also turn this PR into a draft if you want https://github.com/llvm/llvm-project/pull/130973 __

[clang] [llvm] [RISCV][MC] Implement MC for Base P extension (PR #123271)

@@ -224,6 +224,13 @@ static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, uint32_t RegNo, return MCDisassembler::Success; } +static DecodeStatus decodeRVPGPRPair(MCInst &Inst, uint32_t RegNo, + uint64_t Address, +

[clang] [llvm] [RISCV][MC] Implement MC for Base P extension (PR #123271)

@@ -582,4 +586,15 @@ unsigned RISCVMCCodeEmitter::getRegReg(const MCInst &MI, unsigned OpNo, return Op | Op1 << 5; } +unsigned RISCVMCCodeEmitter::getRVPGPRPair(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, +

[clang] [llvm] [RISCV] Add sifive-p470 processor (PR #102022)

mshockwave wrote: > > LLVM Buildbot has detected a new failure on builder `flang-x86_64-windows` > > running on `minipc-ryzen-win` while building `clang,llvm` at step 7 > > "test-build-unified-tree-check-flang". > > Full details are available at: > > https://lab.llvm.org/buildbot/#/builders/16

[clang] [llvm] [RISCV][MC] Add assembler support for XRivosVisni (PR #128773)

@@ -1376,6 +1376,13 @@ def HasVendorXqcilo // Rivos Extension(s) +def FeatureVendorXRivosVisni +: RISCVExperimentalExtension<0, 1, "Rivos Vector Small Integer New">; +def HasVendorXRivosVisni +: Predicate<"Subtarget->hasVendorXRivosVisni()">, + AssemblerPredicat

[clang] [llvm] [RISCV][MC] Add assembler support for XRivosVisni (PR #128773)

@@ -1376,6 +1376,13 @@ def HasVendorXqcilo // Rivos Extension(s) +def FeatureVendorXRivosVisni +: RISCVExperimentalExtension<0, 1, "Rivos Vector Small Integer New">; +def HasVendorXRivosVisni +: Predicate<"Subtarget->hasVendorXRivosVisni()">, + AssemblerPredicat

[clang] [llvm] [RISCV] Mark {vl, vtype} as clobber in inline assembly (PR #128636)

mshockwave wrote: I think what @wangpc-pp advocated here (please correct me if I'm wrong) was that user should be responsible annotating these registers as clobbered so that we have more freedom on scheduling when the inline assembly is not using any vector instructions. While other approaches

[clang] [llvm] [MIPS] Add FeatureMSA to i6400 and i6500 cores (PR #134985)

https://github.com/mshockwave approved this pull request. LGTM, thanks https://github.com/llvm/llvm-project/pull/134985 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Use print-enabled-extensions to check the extensions of Andes n45/nx45/a45/ax45 cpus. NFC. (PR #140979)

https://github.com/mshockwave approved this pull request. https://github.com/llvm/llvm-project/pull/140979 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Andes A25/AX25 processor definition (PR #140681)

https://github.com/mshockwave approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/140681 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Andes A25/AX25 processor definition (PR #140681)

@@ -648,6 +648,38 @@ def RP2350_HAZARD3 : RISCVProcessorModel<"rp2350-hazard3", FeatureStdExtZcb, FeatureStdExtZcmp]>; +def ANDES_A25 : RISCVProcessorModel<"andes-a25", +

[clang] [llvm] [RISCV] Add Andes A25/AX25 processor definition (PR #140681)

@@ -648,6 +648,38 @@ def RP2350_HAZARD3 : RISCVProcessorModel<"rp2350-hazard3", FeatureStdExtZcb, FeatureStdExtZcmp]>; +def ANDES_A25 : RISCVProcessorModel<"andes-a25", +

[clang] [llvm] [RISCV] Add Andes A25/AX25 processor definition (PR #140681)

mshockwave wrote: I propose writing `test/Driver/print-enabled-extensions` tests instead for testing extensions. https://github.com/llvm/llvm-project/pull/140681 ___ cfe-commits mailing list cfe-commits@lists.llvm.or

[clang] [llvm] [RISCV] Add Andes A25/AX25 processor definition (PR #140681)

https://github.com/mshockwave edited https://github.com/llvm/llvm-project/pull/140681 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

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