https://github.com/jayfoad created
https://github.com/llvm/llvm-project/pull/78709
That instruction is not supported on GFX12.
Added a testcase which previously crashed without this change.
>From b212d63828ae87b8e40f9d6de7622bc7a14ce48f Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Mon, 30 Oc
https://github.com/jayfoad created
https://github.com/llvm/llvm-project/pull/78711
This was already done for LLVM. This patch just updates the Clang
builtin handling to match.
>From 8ec83bbc08c6a364efda3724d5886dbd568f956f Mon Sep 17 00:00:00 2001
From: Jay Foad
Date: Fri, 19 Jan 2024 13:34:3
jayfoad wrote:
Can you add a GFX12 RUN line to
clang/test/CodeGenOpenCL/builtins-amdgcn-fp8.cl? That will probably require
adding "fp8-conversion-insts" to the GFX12 part of TargetParser.cpp. You can do
this in a separate patch if you want.
https://github.com/llvm/llvm-project/pull/78414
https://github.com/jayfoad closed
https://github.com/llvm/llvm-project/pull/78709
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@@ -0,0 +1,105 @@
+// REQUIRES: amdgpu-registered-target
jayfoad wrote:
Maybe just add these to `test/CodeGenOpenCL/builtins-amdgcn-gfx12-err.cl`
instead of a new file?
https://github.com/llvm/llvm-project/pull/78729
@@ -1348,6 +1348,14 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo
&Info,
MachineMemOperand::MOVolatile;
return true;
}
+ case Intrinsic::amdgcn_global_load_tr: {
jayfoad wrote:
This case should also be handled in getAdrMo
https://github.com/jayfoad approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/79104
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https://github.com/llvm/llvm-project/pull/69355
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https://github.com/jayfoad approved this pull request.
https://github.com/llvm/llvm-project/pull/69483
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https://github.com/llvm/llvm-project/pull/69483
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jayfoad wrote:
> [AMDGPU] make w32i16/w32f16
Typos "v32"
https://github.com/llvm/llvm-project/pull/70484
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Author: Jay Foad
Date: 2021-10-04T09:38:11+01:00
New Revision: d933adeaca7b9c2aa27e7ca35f7dd4ccc6b5985d
URL:
https://github.com/llvm/llvm-project/commit/d933adeaca7b9c2aa27e7ca35f7dd4ccc6b5985d
DIFF:
https://github.com/llvm/llvm-project/commit/d933adeaca7b9c2aa27e7ca35f7dd4ccc6b5985d.diff
LOG:
Author: Jay Foad
Date: 2021-10-04T11:32:16+01:00
New Revision: 566690b067c8175314fa657b899c99bccf96821c
URL:
https://github.com/llvm/llvm-project/commit/566690b067c8175314fa657b899c99bccf96821c
DIFF:
https://github.com/llvm/llvm-project/commit/566690b067c8175314fa657b899c99bccf96821c.diff
LOG:
Author: Jay Foad
Date: 2021-06-23T10:47:43+01:00
New Revision: 157473a58f02b8f2ad12ecbaaa1af32d0342257b
URL:
https://github.com/llvm/llvm-project/commit/157473a58f02b8f2ad12ecbaaa1af32d0342257b
DIFF:
https://github.com/llvm/llvm-project/commit/157473a58f02b8f2ad12ecbaaa1af32d0342257b.diff
LOG:
Author: Jay Foad
Date: 2021-10-29T15:02:58+01:00
New Revision: 1b758925adf6d78c89c70d2673689695e90fa993
URL:
https://github.com/llvm/llvm-project/commit/1b758925adf6d78c89c70d2673689695e90fa993
DIFF:
https://github.com/llvm/llvm-project/commit/1b758925adf6d78c89c70d2673689695e90fa993.diff
LOG:
Author: Jay Foad
Date: 2021-03-05T20:19:11Z
New Revision: fc28f600e558c1344618bda149a068d6162b6f0b
URL:
https://github.com/llvm/llvm-project/commit/fc28f600e558c1344618bda149a068d6162b6f0b
DIFF:
https://github.com/llvm/llvm-project/commit/fc28f600e558c1344618bda149a068d6162b6f0b.diff
LOG: [AMD
Author: Jay Foad
Date: 2021-03-06T09:00:01Z
New Revision: 99682bc039dfec3e30e6e2b97b4b663f412e0d71
URL:
https://github.com/llvm/llvm-project/commit/99682bc039dfec3e30e6e2b97b4b663f412e0d71
DIFF:
https://github.com/llvm/llvm-project/commit/99682bc039dfec3e30e6e2b97b4b663f412e0d71.diff
LOG: Reve
Author: Jay Foad
Date: 2021-12-04T10:32:11Z
New Revision: 2774bad1124215571ab154afcb5478c78cf46344
URL:
https://github.com/llvm/llvm-project/commit/2774bad1124215571ab154afcb5478c78cf46344
DIFF:
https://github.com/llvm/llvm-project/commit/2774bad1124215571ab154afcb5478c78cf46344.diff
LOG: [AMD
https://github.com/jayfoad approved this pull request.
LGTM, thanks!
https://github.com/llvm/llvm-project/pull/66701
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https://github.com/jayfoad approved this pull request.
LGTM, thanks!
https://github.com/llvm/llvm-project/pull/66701
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https://github.com/jayfoad updated
https://github.com/llvm/llvm-project/pull/67536
>From e0571e8b4712e39678218f02d7f5d68755bc85f9 Mon Sep 17 00:00:00 2001
From: Jay Foad
Date: Wed, 27 Sep 2023 11:01:17 +0100
Subject: [PATCH] [AMDGPU] Add GFX11.5 s_singleuse_vdst instruction
---
llvm/lib/Targe
https://github.com/jayfoad closed
https://github.com/llvm/llvm-project/pull/67536
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jayfoad wrote:
I've just tested this on 1 graphics shaders and it seems to make no
difference at all. I tried gfx900 and gfx1100. Can anyone else from the
graphics team confirm this?
https://github.com/llvm/llvm-project/pull/67878
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jayfoad wrote:
I've just tested this on 1 graphics shaders and it seems to make no
difference at all. I tried gfx900 and gfx1100. Can anyone else from the
graphics team confirm this?
https://github.com/llvm/llvm-project/pull/67878
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jayfoad wrote:
> > > I've just tested this on 1 graphics shaders and it seems to make no
> > > difference at all. I tried gfx900 and gfx1100. Can anyone else from the
> > > graphics team confirm this?
> >
> >
> > I can confirm no difference on gfx1102
>
> gfx11 is the same as gfx10, it j
jayfoad wrote:
I've taken another look at this. The patch does not show any benefit from
running another `SIFoldOperands` pass _after_ `SIShrinkInstructions` per se;
you get exactly the same results (modulo a couple of add instructions that have
their operands commuted differently) if you put
jayfoad wrote:
I've taken another look at this. The patch does not show any benefit from
running another `SIFoldOperands` pass _after_ `SIShrinkInstructions` per se;
you get exactly the same results (modulo a couple of add instructions that have
their operands commuted differently) if you put
@@ -8177,6 +8177,64 @@ SDValue TargetLowering::expandFMINNUM_FMAXNUM(SDNode
*Node,
return SDValue();
}
+SDValue TargetLowering::expandFMINIMUM_FMAXIMUM(SDNode *N,
jayfoad wrote:
> Can MIR be valid input for legalizers?
No, sorry, please ignore that part.
@@ -8177,6 +8177,64 @@ SDValue TargetLowering::expandFMINNUM_FMAXNUM(SDNode
*Node,
return SDValue();
}
+SDValue TargetLowering::expandFMINIMUM_FMAXIMUM(SDNode *N,
jayfoad wrote:
> Can MIR be valid input for legalizers?
No, sorry, please ignore that part.
https://github.com/jayfoad updated
https://github.com/llvm/llvm-project/pull/65729
>From 66129acffd34a4b0f2c8a956d88212ed2ee30946 Mon Sep 17 00:00:00 2001
From: Jay Foad
Date: Fri, 8 Sep 2023 10:09:21 +0100
Subject: [PATCH] Clean up strange uses of getAnalysisIfAvailable
After a pass calls add
https://github.com/jayfoad closed
https://github.com/llvm/llvm-project/pull/65729
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jayfoad wrote:
> I guess I don't know how pull requests and reviewing works in github. I
> actually added 3 comments on this patch a several days (or weeks) ago. But
> turns out that they were "pending" because I had only "started review" and
> not found the place to "submit review".
For that
@@ -3280,7 +3280,7 @@ class llvm::gvn::GVNLegacyPass : public FunctionPass {
if (skipFunction(F))
return false;
-auto *LIWP = getAnalysisIfAvailable();
+auto &LIWP = getAnalysis();
jayfoad wrote:
I prefer not to leave it as is - I think eith
@@ -261,7 +261,7 @@ bool VirtRegRewriter::runOnMachineFunction(MachineFunction
&fn) {
Indexes = &getAnalysis();
LIS = &getAnalysis();
VRM = &getAnalysis();
- DebugVars = getAnalysisIfAvailable();
+ DebugVars = &getAnalysis();
jayfoad wrote:
Thanks! Fi
@@ -935,7 +935,7 @@ bool
AArch64ConditionalCompares::runOnMachineFunction(MachineFunction &MF) {
SchedModel = MF.getSubtarget().getSchedModel();
MRI = &MF.getRegInfo();
DomTree = &getAnalysis();
- Loops = getAnalysisIfAvailable();
+ Loops = &getAnalysis();
https://github.com/jayfoad updated
https://github.com/llvm/llvm-project/pull/65193:
>From 0da34437a4ec6604d27808a020f56c6cf3615b21 Mon Sep 17 00:00:00 2001
From: Sheng
Date: Wed, 30 Aug 2023 11:44:23 +0800
Subject: [PATCH] [clang][Sema] Fix a bug when instantiating a lambda with
requires claus
Author: Jay Foad
Date: 2023-07-17T13:06:12+01:00
New Revision: 92542f2a400024e8a878242afe8231e17df345e5
URL:
https://github.com/llvm/llvm-project/commit/92542f2a400024e8a878242afe8231e17df345e5
DIFF:
https://github.com/llvm/llvm-project/commit/92542f2a400024e8a878242afe8231e17df345e5.diff
LOG:
@@ -157,6 +157,27 @@ static uint32_t getLit16Encoding(uint16_t Val, const
MCSubtargetInfo &STI) {
return 255;
}
+static uint32_t getLitBF16Encoding(uint16_t Val) {
+ uint16_t IntImm = getIntInlineImmEncoding(static_cast(Val));
+ if (IntImm != 0)
+return IntImm;
+
+ /
@@ -157,6 +157,27 @@ static uint32_t getLit16Encoding(uint16_t Val, const
MCSubtargetInfo &STI) {
return 255;
}
+static uint32_t getLitBF16Encoding(uint16_t Val) {
+ uint16_t IntImm = getIntInlineImmEncoding(static_cast(Val));
+ if (IntImm != 0)
+return IntImm;
+
+ /
@@ -14,13 +14,14 @@
#define LLVM_CODEGEN_MACHINEBRANCHPROBABILITYINFO_H
#include "llvm/CodeGen/MachineBasicBlock.h"
-#include "llvm/CodeGen/MachinePassManager.h"
#include "llvm/Pass.h"
#include "llvm/Support/BranchProbability.h"
namespace llvm {
-class MachineBranchProb
jayfoad wrote:
> > Did you know that LLVM intentionally does not follow IWYU and favors
> > forward declarations:
> > https://llvm.org/docs/CodingStandards.html#include-as-little-as-possible
>
> Yes, but I actually do not see what part of the mentioned standard' section
> conflicts with the c
jayfoad wrote:
Can you add at least one test for a VMEM (flat or scratch or global or buffer
or image) atomic without return? That should use vscnt on GFX10.
Apart from that the SIInsertWaitcnts.cpp and tests look good to me. I have not
reviewed the clang parts but it looks like @Pierre-vh app
jayfoad wrote:
No further comments.
https://github.com/llvm/llvm-project/pull/79236
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@@ -1534,6 +1534,12 @@ def FeatureISAVersion11_5_1 : FeatureSet<
FeatureVGPRSingleUseHintInsts,
Feature1_5xVGPRs])>;
+def FeatureISAVersion11_5_2 : FeatureSet<
jayfoad wrote:
I don't have a good answer to this except "it's what we normally do". Othe
https://github.com/jayfoad approved this pull request.
LGTM.
Could also update `flang/cmake/modules/AddFlangOffloadRuntime.cmake` but I
don't really know if it's our responsibility to update Flang.
https://github.com/llvm/llvm-project/pull/94534
___
jayfoad wrote:
Is there really a good use case for this? Can you use regular stores to
addrspace(7) instead? @krzysz00
Also, do you really need a separate builtin for every legal type, or is there
some way they can be type-overloaded?
https://github.com/llvm/llvm-project/pull/94576
__
@@ -6,21 +6,21 @@
__attribute__((global))
void kernel(int *out) {
int i = 0;
- out[i++] = threadIdx.x; // CHECK: call noundef i32
@llvm.nvvm.read.ptx.sreg.tid.x()
- out[i++] = threadIdx.y; // CHECK: call noundef i32
@llvm.nvvm.read.ptx.sreg.tid.y()
- out[i++] = threadIdx
@@ -6,21 +6,21 @@
__attribute__((global))
void kernel(int *out) {
int i = 0;
- out[i++] = threadIdx.x; // CHECK: call noundef i32
@llvm.nvvm.read.ptx.sreg.tid.x()
- out[i++] = threadIdx.y; // CHECK: call noundef i32
@llvm.nvvm.read.ptx.sreg.tid.y()
- out[i++] = threadIdx
@@ -785,6 +785,7 @@ enum : unsigned {
EF_AMDGPU_MACH_AMDGCN_GFX1200 = 0x048,
EF_AMDGPU_MACH_AMDGCN_RESERVED_0X49 = 0x049,
EF_AMDGPU_MACH_AMDGCN_GFX1151 = 0x04a,
+ EF_AMDGPU_MACH_AMDGCN_GFX1152 = 0x055,
jayfoad wrote:
This table
https://github.com/jayfoad approved this pull request.
Works for me.
https://github.com/llvm/llvm-project/pull/94639
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https://github.com/jayfoad created
https://github.com/llvm/llvm-project/pull/95373
None
>From 6d326a96d2651f8836b29ff1e3edef022f41549e Mon Sep 17 00:00:00 2001
From: Jay Foad
Date: Thu, 13 Jun 2024 09:46:48 +0100
Subject: [PATCH] [llvm-project] Fix typo "seperate"
---
clang-tools-extra/clang
https://github.com/jayfoad closed
https://github.com/llvm/llvm-project/pull/95373
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jayfoad wrote:
I'll merge to fix the build.
https://github.com/llvm/llvm-project/pull/95637
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https://github.com/jayfoad closed
https://github.com/llvm/llvm-project/pull/95637
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https://github.com/jayfoad edited
https://github.com/llvm/llvm-project/pull/89217
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@@ -5496,6 +5496,9 @@ const char*
AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
NODE_NAME_CASE(LDS)
NODE_NAME_CASE(FPTRUNC_ROUND_UPWARD)
NODE_NAME_CASE(FPTRUNC_ROUND_DOWNWARD)
+ NODE_NAME_CASE(READLANE)
+ NODE_NAME_CASE(READFIRSTLANE)
---
@@ -5496,6 +5496,9 @@ const char*
AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
NODE_NAME_CASE(LDS)
NODE_NAME_CASE(FPTRUNC_ROUND_UPWARD)
NODE_NAME_CASE(FPTRUNC_ROUND_DOWNWARD)
+ NODE_NAME_CASE(READLANE)
+ NODE_NAME_CASE(READFIRSTLANE)
+ NODE_NAME_CA
https://github.com/jayfoad commented:
Does this need IR autoupgrade?
https://github.com/llvm/llvm-project/pull/89217
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jayfoad wrote:
There is a latent problem to do with convergence. If you add a new test case
like this:
```diff
diff --git a/llvm/test/CodeGen/AMDGPU/convergence-tokens.ll
b/llvm/test/CodeGen/AMDGPU/convergence-tokens.ll
index 238f6ab39e83..22995083293d 100644
--- a/llvm/test/CodeGen/AMDGPU/conv
jayfoad wrote:
Previous attempts:
* https://reviews.llvm.org/D84639
* https://reviews.llvm.org/D86154
* https://reviews.llvm.org/D147732
* #87334
https://github.com/llvm/llvm-project/pull/89217
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ht
jayfoad wrote:
AMDGPU changes are fine.
https://github.com/llvm/llvm-project/pull/90391
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jayfoad wrote:
> Compiler messages on HIP SDK for Windows
Please rewrite this to say what the patch does or what problem it fixes.
https://github.com/llvm/llvm-project/pull/97668
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@@ -5386,6 +5386,153 @@ bool
AMDGPULegalizerInfo::legalizeDSAtomicFPIntrinsic(LegalizerHelper &Helper,
return true;
}
+bool AMDGPULegalizerInfo::legalizeLaneOp(LegalizerHelper &Helper,
+ MachineInstr &MI,
+
https://github.com/jayfoad commented:
LGTM overall.
> add f32 pattern to select read/writelane operations
Why would you need this? Don't you legalize f32 to i32?
https://github.com/llvm/llvm-project/pull/89217
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@@ -5386,6 +5386,130 @@ bool
AMDGPULegalizerInfo::legalizeDSAtomicFPIntrinsic(LegalizerHelper &Helper,
return true;
}
+bool AMDGPULegalizerInfo::legalizeLaneOp(LegalizerHelper &Helper,
+ MachineInstr &MI,
+
@@ -5386,6 +5386,153 @@ bool
AMDGPULegalizerInfo::legalizeDSAtomicFPIntrinsic(LegalizerHelper &Helper,
return true;
}
+bool AMDGPULegalizerInfo::legalizeLaneOp(LegalizerHelper &Helper,
+ MachineInstr &MI,
+
https://github.com/jayfoad edited
https://github.com/llvm/llvm-project/pull/89217
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@@ -493,8 +493,8 @@ Value *AMDGPUAtomicOptimizerImpl::buildScan(IRBuilder<> &B,
if (!ST->isWave32()) {
// Combine lane 31 into lanes 32..63.
V = B.CreateBitCast(V, IntNTy);
- Value *const Lane31 = B.CreateIntrinsic(Intrinsic::amdgcn_readlane, {},
-
https://github.com/jayfoad created
https://github.com/llvm/llvm-project/pull/92232
None
>From a02c63497b0d60f55e1846f5a050820082fb5c86 Mon Sep 17 00:00:00 2001
From: Jay Foad
Date: Wed, 15 May 2024 10:04:57 +0100
Subject: [PATCH] Fix typo "indicies"
---
clang/include/clang/AST/VTTBuilder.h
https://github.com/jayfoad closed
https://github.com/llvm/llvm-project/pull/92232
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jayfoad wrote:
> 1. What's the proper way to legalize f16 and bf16 for SDAG case without
> bitcasts ? (I would think "fp_extend -> LaneOp -> Fptrunc" is wrong)
Bitcast to i16, anyext to i32, laneop, trunc to i16, bitcast to original type.
Why wouldn't you use bitcasts?
https://github.com/llv
Author: Jay Foad
Date: 2021-03-17T09:42:21Z
New Revision: 967b64beb4bf953f452a2866716065e8bbcb5d2f
URL:
https://github.com/llvm/llvm-project/commit/967b64beb4bf953f452a2866716065e8bbcb5d2f
DIFF:
https://github.com/llvm/llvm-project/commit/967b64beb4bf953f452a2866716065e8bbcb5d2f.diff
LOG: [AMD
@@ -402,34 +413,30 @@ Value
*AMDGPUAtomicOptimizerImpl::buildReduction(IRBuilder<> &B,
// Reduce within each pair of rows (i.e. 32 lanes).
assert(ST->hasPermLaneX16());
- V = B.CreateBitCast(V, IntNTy);
jayfoad wrote:
Please submit an NFC cleanup patch
@@ -196,8 +208,10 @@ define amdgpu_kernel void @add_i32_constant(ptr
addrspace(1) %out, ptr addrspace
; GFX11W32-NEXT:v_mbcnt_lo_u32_b32 v0, s1, 0
; GFX11W32-NEXT:; implicit-def: $vgpr1
; GFX11W32-NEXT:s_delay_alu instid0(VALU_DEP_1)
-; GFX11W32-NEXT:v_cmpx_eq_
https://github.com/jayfoad created
https://github.com/llvm/llvm-project/pull/112899
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>From 3a3b67f30cde766adaede4cc53bec340fbe5d99f Mon Sep 17 00:00:00 2001
From: Jay Foad
Date: Fri, 18 Oct 2024 13:53:51 +0100
Subject: [PATCH] Fix typo "instrinsic"
---
clang/utils/TableGen/RISCVVEmitter.
https://github.com/jayfoad closed
https://github.com/llvm/llvm-project/pull/112899
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https://github.com/jayfoad approved this pull request.
LGTM. The compiler currently treats it as identical to gfx1152, right?
https://github.com/llvm/llvm-project/pull/113138
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@@ -603,26 +610,30 @@ Generic processor code objects are versioned. See
:ref:`amdgpu-generic-processor
- ``gfx1103``
work-item within this family.
- ``gfx1150``
https://github.com/jayfoad closed
https://github.com/llvm/llvm-project/pull/109399
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https://github.com/jayfoad created
https://github.com/llvm/llvm-project/pull/113559
BuiltinType::LastKind is currently 507 which is close to the current
limit of 511.
>From fe852c49f160d9b76e61f151bc857eb8493a47db Mon Sep 17 00:00:00 2001
From: Jay Foad
Date: Thu, 24 Oct 2024 13:41:31 +0100
S
@@ -839,6 +839,14 @@ Expected
TargetExtType::checkParams(TargetExtType *TTy) {
"target extension type riscv.vector.tuple should have one "
"type parameter and one integer parameter");
+ // Opaque types in the AMDGPU name space.
+ if (TTy->Name == "amdgcn.nam
jayfoad wrote:
> The community doesn't add new builtin types particularly often, so having
> four leftover bits isn't actually that close to the limit for us.
I guess "close" is subjective.
> Is there a problem with keeping this change downstream until we get to the
> limit in community?
No,
https://github.com/jayfoad closed
https://github.com/llvm/llvm-project/pull/113559
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https://github.com/jayfoad closed
https://github.com/llvm/llvm-project/pull/114795
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None
>From bcb149170d1eaf0a177deee63a9dc289dd55892b Mon Sep 17 00:00:00 2001
From: Jay Foad
Date: Mon, 4 Nov 2024 13:46:28 +
Subject: [PATCH] [llvm-project] Fix typo "propogate"
---
clang/test/Analysis/ma
https://github.com/jayfoad closed
https://github.com/llvm/llvm-project/pull/108970
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https://github.com/jayfoad closed
https://github.com/llvm/llvm-project/pull/113691
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https://github.com/jayfoad approved this pull request.
Looks reasonable with the newline fix, but please wait a day in case other
reviewers have comments.
https://github.com/llvm/llvm-project/pull/113614
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https://github.com/llvm/llvm-project/pull/113691
It is simple to create the struct body up front, now that we have
transitioned to opaque pointers.
>From 0fea81c2996a5476fec5681856191d55841e9f0f Mon Sep 17 00:00:00 2001
From: Jay Foad
Date: Fri, 25 Oct 2024
https://github.com/jayfoad edited
https://github.com/llvm/llvm-project/pull/113614
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@@ -15,7 +15,15 @@
AMDGPU_TYPE(Name, Id, SingletonId, Width, Align)
#endif
+#ifndef AMDGPU_NAMED_BARRIER_TYPE
+#define AMDGPU_NAMED_BARRIER_TYPE(Name, Id, SingletonId, Width, Align, Scope) \
+ AMDGPU_TYPE(Name, Id, SingletonId, Width, Align)
+#endif
+
AMDGPU_OPAQUE_PTR_TYP
jayfoad wrote:
> [opt][AMDGPU] Add pass to handle AMDGCN pseudo-intrinsics target specific
> info), start with `llvm.amdgcn.wavefrontsize`
Mismatched parentheses. (Also it's a bit longer than git likes.
https://github.com/llvm/llvm-project/pull/114481
_
https://github.com/jayfoad created
https://github.com/llvm/llvm-project/pull/109656
This will be used in ASTContext::getTypeInfo which needs this
information for all builtin types, not just pointers.
>From 0ef4ea17a711a1ee95080bc1635ae9aa824df596 Mon Sep 17 00:00:00 2001
From: Jay Foad
Date:
https://github.com/jayfoad closed
https://github.com/llvm/llvm-project/pull/109400
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https://github.com/jayfoad created
https://github.com/llvm/llvm-project/pull/109400
Follow up to #109133.
>From ebffad800626acbdb06c74633c0950e24df755c8 Mon Sep 17 00:00:00 2001
From: Jay Foad
Date: Fri, 20 Sep 2024 11:16:23 +0100
Subject: [PATCH] [clang-tools-extra] Use {} instead of std::nu
https://github.com/jayfoad updated
https://github.com/llvm/llvm-project/pull/109400
>From ebffad800626acbdb06c74633c0950e24df755c8 Mon Sep 17 00:00:00 2001
From: Jay Foad
Date: Fri, 20 Sep 2024 11:16:23 +0100
Subject: [PATCH 1/2] [clang-tools-extra] Use {} instead of std::nullopt to
initialize
jayfoad wrote:
> Although, revisiting this now, I still don't understand why they decided to
> include ALL spill opcodes in the prologue, but not only the SGPR spills?
> Clearly, none of the VGPR reloads really belong to the prologue.
>
> At a first glance, changing the isSpill(opcode) to isSG
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