jayfoad wrote:
Typo in subject "**Guard** return ..."?
https://github.com/llvm/llvm-project/pull/71989
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https://github.com/llvm/llvm-project/pull/71710
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https://github.com/llvm/llvm-project/pull/74616
>From 69580e5f77514fecf0aabe2a80c98881f9bd7288 Mon Sep 17 00:00:00 2001
From: Jay Foad
Date: Tue, 7 Feb 2023 16:27:27 +
Subject: [PATCH 1/2] [AMDGPU] Add GFX12 encoding for VINTERP instructions
---
.../Disa
https://github.com/jayfoad updated
https://github.com/llvm/llvm-project/pull/74616
>From 69580e5f77514fecf0aabe2a80c98881f9bd7288 Mon Sep 17 00:00:00 2001
From: Jay Foad
Date: Tue, 7 Feb 2023 16:27:27 +
Subject: [PATCH 1/2] [AMDGPU] Add GFX12 encoding for VINTERP instructions
---
.../Disa
https://github.com/jayfoad closed
https://github.com/llvm/llvm-project/pull/74616
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Author: Jay Foad
Date: 2023-12-07T17:42:37Z
New Revision: fb2b907fbd2c9ac25077dae01d777d884e09a7a4
URL:
https://github.com/llvm/llvm-project/commit/fb2b907fbd2c9ac25077dae01d777d884e09a7a4
DIFF:
https://github.com/llvm/llvm-project/commit/fb2b907fbd2c9ac25077dae01d777d884e09a7a4.diff
LOG: [AAr
jayfoad wrote:
I committed a fix for builds that do not enable AArch64:
fb2b907fbd2c9ac25077dae01d777d884e09a7a4
https://github.com/llvm/llvm-project/pull/74100
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@@ -959,6 +967,32 @@ def : GCNPat <
}
} // let OtherPredicates = [HasShaderCyclesRegister]
+def SIMM24bitPtr : ImmLeaf (Imm);}]
+>;
+
+multiclass SMPrefetchPat {
+ def : GCNPat <
+(smrd_prefetch (SMRDImm i64:$sbase, i32:$offset), timm, timm, (i32
cache_type)),
+(!cas
@@ -959,6 +967,32 @@ def : GCNPat <
}
} // let OtherPredicates = [HasShaderCyclesRegister]
+def SIMM24bitPtr : ImmLeaf (Imm);}]
+>;
+
+multiclass SMPrefetchPat {
+ def : GCNPat <
+(smrd_prefetch (SMRDImm i64:$sbase, i32:$offset), timm, timm, (i32
cache_type)),
+(!cas
https://github.com/jayfoad updated
https://github.com/llvm/llvm-project/pull/74863
>From e406c734609d3cd1ae436084c42c1c63d8af2795 Mon Sep 17 00:00:00 2001
From: Jay Foad
Date: Fri, 8 Dec 2023 14:08:09 +
Subject: [PATCH 1/2] [GlobalISel] Add G_PREFETCH
---
.../CodeGen/GlobalISel/MachineIRB
https://github.com/jayfoad closed
https://github.com/llvm/llvm-project/pull/74863
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@@ -1708,6 +1710,13 @@ bool
SIInsertWaitcnts::insertWaitcntInBlock(MachineFunction &MF,
}
++Iter;
+if (ST->isPreciseMemoryEnabled() && Inst.mayLoadOrStore()) {
+ auto builder =
jayfoad wrote:
Upper case B for Builder.
https://github.com/llv
@@ -388,6 +388,8 @@ class SIInsertWaitcnts : public MachineFunctionPass {
// message.
DenseSet ReleaseVGPRInsts;
+ // bool insertWaitcntAfterMemOp(MachineFunction &MF);
jayfoad wrote:
Remove all the unused code, don't just comment it out.
https://github
@@ -1708,6 +1710,13 @@ bool
SIInsertWaitcnts::insertWaitcntInBlock(MachineFunction &MF,
}
++Iter;
+if (ST->isPreciseMemoryEnabled() && Inst.mayLoadOrStore()) {
+ auto builder =
+ BuildMI(Block, Iter, DebugLoc(), TII->get(AMDGPU::S_WAITCNT))
+
@@ -0,0 +1,222 @@
+; Testing the -amdgpu-precise-memory-op option
+; COM: llc -mtriple=amdgcn -mcpu=hawaii -mattr=+amdgpu-precise-memory-op
-verify-machineinstrs < %s | FileCheck %s -check-prefixes=GFX7
jayfoad wrote:
What is COM: ?
https://github.com/llvm/llvm
@@ -2314,9 +2314,8 @@ void AMDGPUDAGToDAGISel::SelectBRCOND(SDNode *N) {
SDValue VCMP = Cond->getOperand(0);
auto CC = cast(Cond->getOperand(2))->get();
auto *CRHS = dyn_cast(Cond->getOperand(1));
-if ((CC == ISD::SETEQ || CC == ISD::SETNE) && CRHS && CRHS->isZe
@@ -1847,6 +1862,7 @@ bool
SIInsertWaitcnts::runOnMachineFunction(MachineFunction &MF) {
TrackedWaitcntSet.clear();
BlockInfos.clear();
+
jayfoad wrote:
Remove this
https://github.com/llvm/llvm-project/pull/68932
@@ -1708,6 +1710,19 @@ bool
SIInsertWaitcnts::insertWaitcntInBlock(MachineFunction &MF,
}
++Iter;
+if (ST->isPreciseMemoryEnabled() && Inst.mayLoadOrStore()) {
+ auto Builder =
+ BuildMI(Block, Iter, DebugLoc(), TII->get(AMDGPU::S_WAITCNT))
+
@@ -1708,6 +1710,19 @@ bool
SIInsertWaitcnts::insertWaitcntInBlock(MachineFunction &MF,
}
++Iter;
+if (ST->isPreciseMemoryEnabled() && Inst.mayLoadOrStore()) {
+ auto Builder =
+ BuildMI(Block, Iter, DebugLoc(), TII->get(AMDGPU::S_WAITCNT))
+
https://github.com/jayfoad created
https://github.com/llvm/llvm-project/pull/73133
Define target names and ELF numbers for new GFX12 targets gfx1200 and
gfx1201. For now they behave identically to GFX11.
>From 1011b8e7da174146dfb4c9a4bf54468ea021 Mon Sep 17 00:00:00 2001
From: Jay Foad
Da
https://github.com/jayfoad updated
https://github.com/llvm/llvm-project/pull/73133
>From 1011b8e7da174146dfb4c9a4bf54468ea021 Mon Sep 17 00:00:00 2001
From: Jay Foad
Date: Tue, 21 Nov 2023 15:46:04 +
Subject: [PATCH 1/2] [AMDGPU] Define new targets gfx1200 and gfx1201
Define target nam
@@ -1708,6 +1710,19 @@ bool
SIInsertWaitcnts::insertWaitcntInBlock(MachineFunction &MF,
}
++Iter;
+if (ST->isPreciseMemoryEnabled() && Inst.mayLoadOrStore()) {
+ auto Builder =
+ BuildMI(Block, Iter, DebugLoc(), TII->get(AMDGPU::S_WAITCNT))
+
https://github.com/jayfoad updated
https://github.com/llvm/llvm-project/pull/73133
>From 1011b8e7da174146dfb4c9a4bf54468ea021 Mon Sep 17 00:00:00 2001
From: Jay Foad
Date: Tue, 21 Nov 2023 15:46:04 +
Subject: [PATCH 1/2] [AMDGPU] Define new targets gfx1200 and gfx1201
Define target nam
https://github.com/jayfoad updated
https://github.com/llvm/llvm-project/pull/70644
>From bfc7b2041f5a05105808b0b1ee0427d9c9eb9f4b Mon Sep 17 00:00:00 2001
From: Jay Foad
Date: Mon, 30 Oct 2023 15:23:48 +
Subject: [PATCH 1/4] Precommit test
---
.../AMDGPU/fix-sgpr-copies-nondeterminism.ll
https://github.com/jayfoad closed
https://github.com/llvm/llvm-project/pull/70644
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> Should we move on and submit this patch?
Yes!
> @jayfoad do you have concerns about live-through register set computation or
> others?
I personally have no interest in the live-through part. You could remove it
from this patch, but I d
@@ -290,37 +291,40 @@ bool SIFoldOperands::updateOperand(FoldCandidate &Fold)
const {
if (Fold.Commuted)
TII->commuteInstruction(*Inst32, false);
-return true;
- }
- assert(!Fold.needsShrink() && "not handled");
+Fold.UseMI = Inst32;
+Fold.UseOpNo =
https://github.com/jayfoad converted_to_draft
https://github.com/llvm/llvm-project/pull/68426
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https://github.com/llvm/llvm-project/pull/70235
>From e02640686a8cf0a42cec01da4f32b6888f5de11f Mon Sep 17 00:00:00 2001
From: Jay Foad
Date: Wed, 25 Oct 2023 17:14:40 +0100
Subject: [PATCH 1/2] [AMDGPU] New ttracedata intrinsics
Add llvm.amdgcn.s.ttracedata a
https://github.com/jayfoad closed
https://github.com/llvm/llvm-project/pull/70235
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Author: Jay Foad
Date: 2023-12-13T10:49:52Z
New Revision: effd47ed45e3badd756103346a7c3b9e1e939e5e
URL:
https://github.com/llvm/llvm-project/commit/effd47ed45e3badd756103346a7c3b9e1e939e5e
DIFF:
https://github.com/llvm/llvm-project/commit/effd47ed45e3badd756103346a7c3b9e1e939e5e.diff
LOG: [Cla
@@ -0,0 +1,134 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 3
+
+// RUN: %clang_cc1 -DSVE_HEADER -triple aarch64 -target-feature +sve
-emit-llvm -O2 -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s
+// RUN: %clang_cc1
@@ -0,0 +1,154 @@
+; RUN: llc -march=amdgcn -mcpu=gfx900 < %s | FileCheck %s
--check-prefixeses=GCN,GFX9
+; RUN: llc -march=amdgcn -mcpu=gfx1030 < %s | FileCheck %s
--check-prefixeses=GCN,GFX10
jayfoad wrote:
> --check-prefixeses
That's what happens when you e
jayfoad wrote:
Please remember to add a suitable `REQUIRES:` line to these new codegen tests,
or put them in an `ARM` subdirectory with a suitable `lit.local.cfg`!
This new test is failing in non-ARM builds with:
```
FAIL: Clang :: CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_qrshr.c (5567 of
Author: Jay Foad
Date: 2023-12-14T13:20:37Z
New Revision: 50e78de76a5e77e15ddea48dfb520d6bbcbc1c45
URL:
https://github.com/llvm/llvm-project/commit/50e78de76a5e77e15ddea48dfb520d6bbcbc1c45
DIFF:
https://github.com/llvm/llvm-project/commit/50e78de76a5e77e15ddea48dfb520d6bbcbc1c45.diff
LOG: [AAr
jayfoad wrote:
> Please remember to add a suitable `REQUIRES:` line to these new codegen tests
I've added one in 50e78de76a5e77e15ddea48dfb520d6bbcbc1c45
https://github.com/llvm/llvm-project/pull/75325
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@@ -684,6 +684,51 @@ s_rndne_f16 s5, 0xfe0b
s_rndne_f16 s5, 0x3456
// GFX12: encoding: [0xff,0x6e,0x85,0xbe,0x56,0x34,0x00,0x00]
+s_barrier_signal -2
jayfoad wrote:
Missing `s_get_barrier_state` tests in this file?
https://github.com/llvm/llvm-project/pull/7
@@ -3164,6 +3164,18 @@ def : GCNPat <
(as_i1timm $bound_ctrl))
>;
+class SMPrefetchGetPcPat : GCNPat <
jayfoad wrote:
This pattern also interprets the "address" argument as being an offset from PC,
so it should also be removed from th
jayfoad wrote:
The new test is crashing in my Release+Asserts build:
```
FAIL: Clang :: Driver/riscv-toolchain-gcc-multilib-reuse.c (1081 of 1081)
TEST 'Clang ::
Driver/riscv-toolchain-gcc-multilib-reuse.c' FAILED
Exit Code: 2
Command Output (stderr):
-
jayfoad wrote:
> Use PoisonValue instead of nullptr for load memop as a Value.
What is the effect of that? I thought nullptr was supposed to represent an
unknown value, so you have to conservatively assume it might alias with
anything.
https://github.com/llvm/llvm-project/pull/75247
_
jayfoad wrote:
How does this work in a case like this?
```
call void @llvm.amdgcn.raw.buffer.load.lds(<4 x i32> %rsrc, ptr addrspace(3)
@lds.3, i32 4, i32 0, i32 0, i32 0, i32 0)
call void @llvm.amdgcn.raw.buffer.load.lds(<4 x i32> %rsrc, ptr addrspace(3)
%ptr, i32 4, i32 0, i32 0, i32 0, i32 0
jayfoad wrote:
> > How does this work in a case like this?
> > ```
> > call void @llvm.amdgcn.raw.buffer.load.lds(<4 x i32> %rsrc, ptr
> > addrspace(3) @lds.3, i32 4, i32 0, i32 0, i32 0, i32 0)
> > call void @llvm.amdgcn.raw.buffer.load.lds(<4 x i32> %rsrc, ptr
> > addrspace(3) %ptr, i32 4, i3
https://github.com/jayfoad closed
https://github.com/llvm/llvm-project/pull/73133
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jayfoad wrote:
Hi, on my Release+Asserts build this is causing:
```
FAIL: Clang-Unit ::
Analysis/FlowSensitive/./ClangAnalysisFlowSensitiveTests/32/38 (134 of 658)
TEST 'Clang-Unit ::
Analysis/FlowSensitive/./ClangAnalysisFlowSensitiveTests/32/38' FAILED
**
https://github.com/jayfoad approved this pull request.
LGTM but the commit message should really explain what problem this fixes
instead of just saying "rework".
https://github.com/llvm/llvm-project/pull/74293
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jayfoad wrote:
> The referenced issue violates the spec for finite-only math only by
> using a return value for a constant infinity.
You mean this issue?
https://github.com/llvm/llvm-project/commit/5a36904c515b#commitcomment-129847939
Can you explain how your patch "broke" it? If you return in
https://github.com/jayfoad updated
https://github.com/llvm/llvm-project/pull/76149
>From b14a554a15e4de88c9afc428f9c6898090e6eb23 Mon Sep 17 00:00:00 2001
From: Jay Foad
Date: Thu, 21 Dec 2023 12:00:26 +
Subject: [PATCH] [AMDGPU] GFX12 global_atomic_ordered_add_b64 instruction and
intrinsi
jayfoad wrote:
Ping!
https://github.com/llvm/llvm-project/pull/76149
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https://github.com/jayfoad closed
https://github.com/llvm/llvm-project/pull/76149
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https://github.com/jayfoad approved this pull request.
LGTM. @arsenm does this address your concerns?
https://github.com/llvm/llvm-project/pull/76212
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https://github.com/jayfoad updated
https://github.com/llvm/llvm-project/pull/75220
>From 429d0a22cd4208eb0c854ccf98df1ba86fd3b0cb Mon Sep 17 00:00:00 2001
From: Jay Foad
Date: Tue, 12 Dec 2023 17:15:26 +
Subject: [PATCH] [AMDGPU] Flip the default value of maybeAtomic. NFCI.
In practice may
https://github.com/jayfoad closed
https://github.com/llvm/llvm-project/pull/75220
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@@ -29,6 +29,7 @@ class SM_Pseudo patt
let mayStore = 0;
let mayLoad = 1;
let hasSideEffects = 0;
+ let maybeAtomic = 0;
jayfoad wrote:
#77443
https://github.com/llvm/llvm-project/pull/75220
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https://github.com/llvm/llvm-project/pull/77470
>From ae231d88c5b5e2e0996edefd45389992f8e97d05 Mon Sep 17 00:00:00 2001
From: Jay Foad
Date: Tue, 9 Jan 2024 13:16:24 +
Subject: [PATCH 1/3] [AMDGPU] Precommit tests for broken combine
Add tests for sign-ext
https://github.com/jayfoad closed
https://github.com/llvm/llvm-project/pull/77470
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Author: Jay Foad
Date: 2022-05-19T11:23:13+01:00
New Revision: 6bec3e9303d68b8b264de3a02ca943d9dd752004
URL:
https://github.com/llvm/llvm-project/commit/6bec3e9303d68b8b264de3a02ca943d9dd752004
DIFF:
https://github.com/llvm/llvm-project/commit/6bec3e9303d68b8b264de3a02ca943d9dd752004.diff
LOG:
@@ -2326,6 +2326,20 @@ bool
SIInsertWaitcnts::insertWaitcntInBlock(MachineFunction &MF,
}
#endif
+if (ST->isPreciseMemoryEnabled() && Inst.mayLoadOrStore()) {
+ AMDGPU::Waitcnt Wait;
+ if (ST->hasExtendedWaitCounts())
+Wait = AMDGPU::Waitcnt(0, 0, 0,
@@ -2326,6 +2326,20 @@ bool
SIInsertWaitcnts::insertWaitcntInBlock(MachineFunction &MF,
}
#endif
+if (ST->isPreciseMemoryEnabled() && Inst.mayLoadOrStore()) {
+ AMDGPU::Waitcnt Wait;
+ if (ST->hasExtendedWaitCounts())
+Wait = AMDGPU::Waitcnt(0, 0, 0,
@@ -2594,12 +2594,10 @@ bool SIMemoryLegalizer::expandAtomicCmpxchgOrRmw(const
SIMemOpInfo &MOI,
MOI.getOrdering() == AtomicOrdering::SequentiallyConsistent ||
MOI.getFailureOrdering() == AtomicOrdering::Acquire ||
MOI.getFailureOrdering() == AtomicOrde
@@ -0,0 +1,1406 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=+precise-memory < %s |
FileCheck %s -check-prefixes=GFX9
+; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -mattr=+preci
@@ -0,0 +1,1406 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=+precise-memory < %s |
FileCheck %s -check-prefixes=GFX9
+; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -mattr=+preci
jayfoad wrote:
> This logic would need updating again for GFX12. It seems like it's
> duplicating a lot of knowledge which is already implemented in
> SIInsertWaitcnts.
Just to demonstrate, you could implement this feature in SIInsertWaitcnts for
**all** supported architectures with something
https://github.com/jayfoad requested changes to this pull request.
I've added _some_ inline comments, but really I don't want to spend the time to
review this properly (or maintain it, or extend it for new architectures in
future). All this logic already exists in SIInsertWaitcnts. Duplicating
@@ -2378,6 +2409,215 @@ bool
SIGfx12CacheControl::enableVolatileAndOrNonTemporal(
return Changed;
}
+bool SIGfx6CacheControl::handleNonAtomicForPreciseMemory(
+MachineBasicBlock::iterator &MI) {
+ assert(MI->mayLoadOrStore());
+
+ MachineInstr &Inst = *MI;
+ AMDGPU::
@@ -2378,6 +2409,215 @@ bool
SIGfx12CacheControl::enableVolatileAndOrNonTemporal(
return Changed;
}
+bool SIGfx6CacheControl::handleNonAtomicForPreciseMemory(
+MachineBasicBlock::iterator &MI) {
+ assert(MI->mayLoadOrStore());
+
+ MachineInstr &Inst = *MI;
+ AMDGPU::
https://github.com/jayfoad edited
https://github.com/llvm/llvm-project/pull/79236
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@@ -355,6 +356,18 @@ class SICacheControl {
MachineBasicBlock::iterator &MI) const {
return false;
}
+
+public:
+ // The following is for supporting precise memory mode. When the feature
+ // precise-memory is enabled, an s_waitcnt ins
jayfoad wrote:
After this change is there any value in having two different builtins? You
could just have one that always return 64 bits.
https://github.com/llvm/llvm-project/pull/80183
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https://github.com/jayfoad closed
https://github.com/llvm/llvm-project/pull/79980
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@@ -2561,6 +2567,70 @@ bool SIMemoryLegalizer::expandAtomicCmpxchgOrRmw(const
SIMemOpInfo &MOI,
return Changed;
}
+bool SIMemoryLegalizer::GFX9InsertWaitcntForPreciseMem(MachineFunction &MF) {
+ const GCNSubtarget &ST = MF.getSubtarget();
+ const SIInstrInfo *TII = ST.get
https://github.com/jayfoad edited
https://github.com/llvm/llvm-project/pull/78729
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https://github.com/jayfoad approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/78729
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@@ -4,10 +4,114 @@
typedef unsigned int uint;
-kernel void test_builtins_amdgcn_gws_insts(uint a, uint b) {
+#pragma OPENCL EXTENSION cl_khr_fp64:enable
+
+typedef float v2f __attribute__((ext_vector_type(2)));
+typedef float v4f __attribute__((ext_vector_type(4)));
+ty
https://github.com/jayfoad updated
https://github.com/llvm/llvm-project/pull/78740
>From c7636536d65a3792223e083dc5bacd0a8e6ff3d7 Mon Sep 17 00:00:00 2001
From: Jay Foad
Date: Fri, 19 Jan 2024 16:06:00 +
Subject: [PATCH] [AMDGPU] Update SITargetLowering::getAddrModeArguments
Handle every i
jayfoad wrote:
> Also need to be updated:
>
> https://github.com/llvm/llvm-project/blob/bb6a4850553dd4140a5bd63187ec1b14d0b731f9/llvm/lib/Target/AMDGPU/SMInstructions.td#L14
What needs to be updated and why?
https://github.com/llvm/llvm-project/pull/77795
__
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https://github.com/llvm/llvm-project/pull/68426
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jayfoad wrote:
> @jayfoad, can you link to the documentation where these new registers are
> described? Preferably from a comment in the top of the file(s). It would make
> it easier to review for correctness.
ISA documentation will be linked from
https://llvm.org/docs/AMDGPUUsage.html#additi
https://github.com/jayfoad created
https://github.com/llvm/llvm-project/pull/79980
None
>From cace712a8f379df3498dd76bc1f95eb4671e997c Mon Sep 17 00:00:00 2001
From: Jay Foad
Date: Tue, 30 Jan 2024 11:04:33 +
Subject: [PATCH] [AMDGPU] Check wavefrontsize for GFX11 WMMA builtins
---
clang
@@ -21,14 +21,14 @@ void test_amdgcn_wmma_f32_16x16x16_bf16_w64(global v4f*
out4f, v16h a16h, v16h b
global v8s* out8s, v4i a4i, v4i
b4i, v8s c8s,
global v4i* out4i, v2i a2i, v2i
b2i, v4i
jayfoad wrote:
> Do you think it makes sense to add two gfx11 tests where _w32 variant is now
> rejected with w64, and _w64 variant rejected with w32?
Maybe, but i didn't have the energy to add yet more tests.
> Maybe what is being printed in *-gfx10-err.cl test is enough, though.
Right, that
https://github.com/jayfoad created
https://github.com/llvm/llvm-project/pull/77926
None
>From 3d4b8547514f2315130599230e769a8c73be01c3 Mon Sep 17 00:00:00 2001
From: Jay Foad
Date: Fri, 12 Jan 2024 12:43:16 +
Subject: [PATCH] [AMDGPU] Add GFX12 __builtin_amdgcn_s_sleep_var
---
clang/incl
jayfoad wrote:
> Adding support in atomicrmw. This will require to add new operation to
> aromicrmw "cond_sub"
Yes, and we have (Matt has) done this in the past, but it will require a wider
consensus. I think it's fine to add AMDGPU intrinsics for this in the mean time.
https://github.com/llv
https://github.com/jayfoad updated
https://github.com/llvm/llvm-project/pull/77927
>From 3f3bcdb89adf032e26c95807abf5e3b23ff50e4a Mon Sep 17 00:00:00 2001
From: Jay Foad
Date: Fri, 12 Jan 2024 12:24:28 +
Subject: [PATCH 1/2] Precommit extra GFX12 test coverage
---
.../GlobalISel/inst-sele
https://github.com/jayfoad updated
https://github.com/llvm/llvm-project/pull/77927
>From 3f3bcdb89adf032e26c95807abf5e3b23ff50e4a Mon Sep 17 00:00:00 2001
From: Jay Foad
Date: Fri, 12 Jan 2024 12:24:28 +
Subject: [PATCH 1/3] Precommit extra GFX12 test coverage
---
.../GlobalISel/inst-sele
https://github.com/jayfoad updated
https://github.com/llvm/llvm-project/pull/78191
>From 9990fbc26ed3dc245a5127345326050acac49d66 Mon Sep 17 00:00:00 2001
From: Jay Foad
Date: Fri, 21 Apr 2023 10:46:43 +0100
Subject: [PATCH] [AMDGPU] Fix llvm.amdgcn.s.wait.event.export.ready for GFX12
The mean
https://github.com/jayfoad closed
https://github.com/llvm/llvm-project/pull/77927
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https://github.com/jayfoad closed
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https://github.com/jayfoad updated
https://github.com/llvm/llvm-project/pull/77929
>From 4299ba898449f782c642b0c27f0ec9970aee0a1c Mon Sep 17 00:00:00 2001
From: Jay Foad
Date: Fri, 12 Jan 2024 11:34:02 +
Subject: [PATCH 1/2] [AMDGPU] Src1 of VOP3 DPP instructions can be SGPR on
GFX12
---
jayfoad wrote:
@Pierre-vh @arsen ping! (Sorry, I know it has only been a few days.)
https://github.com/llvm/llvm-project/pull/77438
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https://github.com/jayfoad closed
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https://github.com/jayfoad updated
https://github.com/llvm/llvm-project/pull/78186
>From d3f4ebf849f6ef1ea373e5c7f93398db6681b2b6 Mon Sep 17 00:00:00 2001
From: Jay Foad
Date: Mon, 15 Jan 2024 15:02:08 +
Subject: [PATCH 1/4] Add GFX11/12 test coverage
---
llvm/test/CodeGen/AMDGPU/s-getpc-
https://github.com/jayfoad closed
https://github.com/llvm/llvm-project/pull/77926
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https://github.com/jayfoad updated
https://github.com/llvm/llvm-project/pull/78186
>From d3f4ebf849f6ef1ea373e5c7f93398db6681b2b6 Mon Sep 17 00:00:00 2001
From: Jay Foad
Date: Mon, 15 Jan 2024 15:02:08 +
Subject: [PATCH 1/4] Add GFX11/12 test coverage
---
llvm/test/CodeGen/AMDGPU/s-getpc-
https://github.com/jayfoad closed
https://github.com/llvm/llvm-project/pull/78186
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@@ -1,7 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck
--check-prefixes=SI %s
jayfoad wrote:
Done as part of a merge from main to fix conflicts.
https://github.com/jayfoad closed
https://github.com/llvm/llvm-project/pull/78155
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jayfoad wrote:
Some of the tests in this patch need regenerating now that #77438 has been
merged.
https://github.com/llvm/llvm-project/pull/77795
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