Author: Heejin Ahn
Date: 2020-09-08T09:22:22-07:00
New Revision: 71133e8b5bceaf68a2cee59af371df570a1aed79
URL:
https://github.com/llvm/llvm-project/commit/71133e8b5bceaf68a2cee59af371df570a1aed79
DIFF:
https://github.com/llvm/llvm-project/commit/71133e8b5bceaf68a2cee59af371df570a1aed79.diff
LO
Author: Heejin Ahn
Date: 2020-11-13T11:57:09-08:00
New Revision: 01d87153694052d1712e9d539b7cc1425c3aff30
URL:
https://github.com/llvm/llvm-project/commit/01d87153694052d1712e9d539b7cc1425c3aff30
DIFF:
https://github.com/llvm/llvm-project/commit/01d87153694052d1712e9d539b7cc1425c3aff30.diff
LO
Author: Heejin Ahn
Date: 2020-11-13T12:04:48-08:00
New Revision: 902ea588eab849e7254d3bc76abf32d833ac0dd6
URL:
https://github.com/llvm/llvm-project/commit/902ea588eab849e7254d3bc76abf32d833ac0dd6
DIFF:
https://github.com/llvm/llvm-project/commit/902ea588eab849e7254d3bc76abf32d833ac0dd6.diff
LO
Author: Heejin Ahn
Date: 2020-10-28T10:01:21-07:00
New Revision: 98941279b90ee096a7d34f09d320d8e1d5fcb61b
URL:
https://github.com/llvm/llvm-project/commit/98941279b90ee096a7d34f09d320d8e1d5fcb61b
DIFF:
https://github.com/llvm/llvm-project/commit/98941279b90ee096a7d34f09d320d8e1d5fcb61b.diff
LO
Author: Heejin Ahn
Date: 2021-05-20T13:00:20-07:00
New Revision: 3eb12b0ae11fe23dc06e55e526fb45e460f72f1e
URL:
https://github.com/llvm/llvm-project/commit/3eb12b0ae11fe23dc06e55e526fb45e460f72f1e
DIFF:
https://github.com/llvm/llvm-project/commit/3eb12b0ae11fe23dc06e55e526fb45e460f72f1e.diff
LO
Author: Heejin Ahn
Date: 2021-02-17T16:10:59-08:00
New Revision: 0b5d2b0efd3eb9a6c1d454a7fc50942e906f522c
URL:
https://github.com/llvm/llvm-project/commit/0b5d2b0efd3eb9a6c1d454a7fc50942e906f522c
DIFF:
https://github.com/llvm/llvm-project/commit/0b5d2b0efd3eb9a6c1d454a7fc50942e906f522c.diff
LO
Author: Heejin Ahn
Date: 2021-03-04T14:26:35-08:00
New Revision: 561abd83ffecc8d4ba8fcbbbcadb31efc55985c2
URL:
https://github.com/llvm/llvm-project/commit/561abd83ffecc8d4ba8fcbbbcadb31efc55985c2
DIFF:
https://github.com/llvm/llvm-project/commit/561abd83ffecc8d4ba8fcbbbcadb31efc55985c2.diff
LO
Author: Heejin Ahn
Date: 2023-09-22T00:35:37-07:00
New Revision: 058222b2316615194c089f2bc68d11341f39d26e
URL:
https://github.com/llvm/llvm-project/commit/058222b2316615194c089f2bc68d11341f39d26e
DIFF:
https://github.com/llvm/llvm-project/commit/058222b2316615194c089f2bc68d11341f39d26e.diff
LO
aheejin wrote:
> > Can you point out what are the unsupported options here?
>
> All of them, they are all options that translate to TargetOptions, and they
> do nothing for a wasm target triple: ` --trap-unreachable=false
> --xcoff-traceback-table=true --relax-elf-relocations=false --vec-extab
aheejin wrote:
> > Can you point out what are the unsupported options here?
>
> All of them, they are all options that translate to TargetOptions, and they
> do nothing for a wasm target triple: ` --trap-unreachable=false
> --xcoff-traceback-table=true --relax-elf-relocations=false --vec-extab
aheejin wrote:
> There's no difference between "doing nothing with respect to it" and
> "silently rejecting", it's the same thing. The wasm backend understands
> neither --xcoff-traceback-table, --trap-unreachable, _or_
> --no-trap-after-noreturn (the fact that --no-trap-after-noreturn affects
@@ -1,33 +1,133 @@
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs | FileCheck %s
-; RUN: llc < %s -asm-verbose=false -fast-isel -fast-isel-abort=1
-verify-machineinstrs | FileCheck %s
-
-; Test that LLVM unreachable instruction and trap intrinsic are lowered to
-; wasm
@@ -1,33 +1,133 @@
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs | FileCheck %s
-; RUN: llc < %s -asm-verbose=false -fast-isel -fast-isel-abort=1
-verify-machineinstrs | FileCheck %s
-
-; Test that LLVM unreachable instruction and trap intrinsic are lowered to
-; wasm
@@ -1,33 +1,133 @@
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs | FileCheck %s
-; RUN: llc < %s -asm-verbose=false -fast-isel -fast-isel-abort=1
-verify-machineinstrs | FileCheck %s
-
-; Test that LLVM unreachable instruction and trap intrinsic are lowered to
-; wasm
@@ -1,33 +1,133 @@
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs | FileCheck %s
-; RUN: llc < %s -asm-verbose=false -fast-isel -fast-isel-abort=1
-verify-machineinstrs | FileCheck %s
-
-; Test that LLVM unreachable instruction and trap intrinsic are lowered to
-; wasm
@@ -1,33 +1,133 @@
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs | FileCheck %s
-; RUN: llc < %s -asm-verbose=false -fast-isel -fast-isel-abort=1
-verify-machineinstrs | FileCheck %s
-
-; Test that LLVM unreachable instruction and trap intrinsic are lowered to
-; wasm
@@ -1,33 +1,133 @@
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs | FileCheck %s
-; RUN: llc < %s -asm-verbose=false -fast-isel -fast-isel-abort=1
-verify-machineinstrs | FileCheck %s
-
-; Test that LLVM unreachable instruction and trap intrinsic are lowered to
-; wasm
@@ -1,33 +1,133 @@
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs | FileCheck %s
-; RUN: llc < %s -asm-verbose=false -fast-isel -fast-isel-abort=1
-verify-machineinstrs | FileCheck %s
-
-; Test that LLVM unreachable instruction and trap intrinsic are lowered to
-; wasm
@@ -1,33 +1,133 @@
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs | FileCheck %s
-; RUN: llc < %s -asm-verbose=false -fast-isel -fast-isel-abort=1
-verify-machineinstrs | FileCheck %s
-
-; Test that LLVM unreachable instruction and trap intrinsic are lowered to
-; wasm
@@ -1,33 +1,133 @@
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs | FileCheck %s
-; RUN: llc < %s -asm-verbose=false -fast-isel -fast-isel-abort=1
-verify-machineinstrs | FileCheck %s
-
-; Test that LLVM unreachable instruction and trap intrinsic are lowered to
-; wasm
https://github.com/aheejin edited
https://github.com/llvm/llvm-project/pull/65876
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aheejin wrote:
> > But `--no-trap-after-noreturn` didn't exist before, so there was no way to
> > specify that from the command line. You _created_ it, originally in this
> > PR, and then the split-off PR in #67051. If this is a bugfix, it sounds
> > like you are fixing a bug of your own makin
aheejin wrote:
> Yeah you've got it, that's the main point. It can be set via the C++ API, and
> when I tried doing so in the Rust compiler I found it broke the WebAssembly
> backend. Sorry if I didn't make that clear enough earlier, I'm glad we're on
> the same page now.
The other points I t
https://github.com/aheejin created
https://github.com/llvm/llvm-project/pull/67770
This was missing when the file was added.
>From 3277e2c8058c5d9b0afcc073d711646ebbf7ed62 Mon Sep 17 00:00:00 2001
From: Heejin Ahn
Date: Thu, 28 Sep 2023 23:43:26 -0700
Subject: [PATCH] [libunwind] Add Unwind-wa
https://github.com/aheejin updated
https://github.com/llvm/llvm-project/pull/67770
>From 3277e2c8058c5d9b0afcc073d711646ebbf7ed62 Mon Sep 17 00:00:00 2001
From: Heejin Ahn
Date: Thu, 28 Sep 2023 23:43:26 -0700
Subject: [PATCH 1/2] [libunwind] Add Unwind-wasm.c to CMakeLists.txt
This was missin
aheejin wrote:
> > Yeah I get that we haven't been warning about a similar case
> > (--trap-unreachable) before. But I think they are more of what ended up
> > happen, and not the firm intention not to warn for conflicted requests.
> > For example, that --trap-unreachable command line option wa
@@ -1,33 +1,133 @@
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs | FileCheck %s
-; RUN: llc < %s -asm-verbose=false -fast-isel -fast-isel-abort=1
-verify-machineinstrs | FileCheck %s
-
-; Test that LLVM unreachable instruction and trap intrinsic are lowered to
-; wasm
https://github.com/aheejin edited
https://github.com/llvm/llvm-project/pull/67770
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aheejin wrote:
> > This was missing when the file was added.
>
> Please reference the commit
> [058222b](https://github.com/llvm/llvm-project/commit/058222b2316615194c089f2bc68d11341f39d26e)
Done.
https://github.com/llvm/llvm-project/pull/67770
___
https://github.com/aheejin updated
https://github.com/llvm/llvm-project/pull/67770
>From 3277e2c8058c5d9b0afcc073d711646ebbf7ed62 Mon Sep 17 00:00:00 2001
From: Heejin Ahn
Date: Thu, 28 Sep 2023 23:43:26 -0700
Subject: [PATCH 1/3] [libunwind] Add Unwind-wasm.c to CMakeLists.txt
This was missin
https://github.com/aheejin updated
https://github.com/llvm/llvm-project/pull/67770
>From 3277e2c8058c5d9b0afcc073d711646ebbf7ed62 Mon Sep 17 00:00:00 2001
From: Heejin Ahn
Date: Thu, 28 Sep 2023 23:43:26 -0700
Subject: [PATCH 1/4] [libunwind] Add Unwind-wasm.c to CMakeLists.txt
This was missin
https://github.com/aheejin updated
https://github.com/llvm/llvm-project/pull/67770
>From 3277e2c8058c5d9b0afcc073d711646ebbf7ed62 Mon Sep 17 00:00:00 2001
From: Heejin Ahn
Date: Thu, 28 Sep 2023 23:43:26 -0700
Subject: [PATCH 1/5] [libunwind] Add Unwind-wasm.c to CMakeLists.txt
This was missin
https://github.com/aheejin updated
https://github.com/llvm/llvm-project/pull/67770
>From 3277e2c8058c5d9b0afcc073d711646ebbf7ed62 Mon Sep 17 00:00:00 2001
From: Heejin Ahn
Date: Thu, 28 Sep 2023 23:43:26 -0700
Subject: [PATCH 1/6] [libunwind] Add Unwind-wasm.c to CMakeLists.txt
This was missin
https://github.com/aheejin edited
https://github.com/llvm/llvm-project/pull/67770
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aheejin wrote:
Will merge this; the remaining CI failures don't seem to related.
https://github.com/llvm/llvm-project/pull/67770
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@@ -1,33 +1,151 @@
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs | FileCheck %s
-; RUN: llc < %s -asm-verbose=false -fast-isel -fast-isel-abort=1
-verify-machineinstrs | FileCheck %s
+; The assertions in this file were autogenerated by
+; utils/update_llc_test_checks.
@@ -1,33 +1,151 @@
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs | FileCheck %s
-; RUN: llc < %s -asm-verbose=false -fast-isel -fast-isel-abort=1
-verify-machineinstrs | FileCheck %s
+; The assertions in this file were autogenerated by
+; utils/update_llc_test_checks.
@@ -1,33 +1,151 @@
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs | FileCheck %s
-; RUN: llc < %s -asm-verbose=false -fast-isel -fast-isel-abort=1
-verify-machineinstrs | FileCheck %s
+; The assertions in this file were autogenerated by
+; utils/update_llc_test_checks.
@@ -1,33 +1,151 @@
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs | FileCheck %s
-; RUN: llc < %s -asm-verbose=false -fast-isel -fast-isel-abort=1
-verify-machineinstrs | FileCheck %s
+; The assertions in this file were autogenerated by
+; utils/update_llc_test_checks.
@@ -1,33 +1,151 @@
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs | FileCheck %s
-; RUN: llc < %s -asm-verbose=false -fast-isel -fast-isel-abort=1
-verify-machineinstrs | FileCheck %s
+; The assertions in this file were autogenerated by
+; utils/update_llc_test_checks.
@@ -1,33 +1,151 @@
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs | FileCheck %s
-; RUN: llc < %s -asm-verbose=false -fast-isel -fast-isel-abort=1
-verify-machineinstrs | FileCheck %s
+; The assertions in this file were autogenerated by
+; utils/update_llc_test_checks.
@@ -1,33 +1,151 @@
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs | FileCheck %s
-; RUN: llc < %s -asm-verbose=false -fast-isel -fast-isel-abort=1
-verify-machineinstrs | FileCheck %s
+; The assertions in this file were autogenerated by
+; utils/update_llc_test_checks.
@@ -1,33 +1,151 @@
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs | FileCheck %s
-; RUN: llc < %s -asm-verbose=false -fast-isel -fast-isel-abort=1
-verify-machineinstrs | FileCheck %s
+; The assertions in this file were autogenerated by
+; utils/update_llc_test_checks.
@@ -1,33 +1,151 @@
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs | FileCheck %s
-; RUN: llc < %s -asm-verbose=false -fast-isel -fast-isel-abort=1
-verify-machineinstrs | FileCheck %s
+; The assertions in this file were autogenerated by
+; utils/update_llc_test_checks.
@@ -1,33 +1,151 @@
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs | FileCheck %s
-; RUN: llc < %s -asm-verbose=false -fast-isel -fast-isel-abort=1
-verify-machineinstrs | FileCheck %s
+; The assertions in this file were autogenerated by
+; utils/update_llc_test_checks.
https://github.com/aheejin edited
https://github.com/llvm/llvm-project/pull/65876
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@@ -6,12 +6,8 @@
; "end_function" lines intact when you commit.
-; --trap-unreachable and --no-trap-after-noreturn are sensitive and bug-prone
-; options for the WebAssembly back-end as, unlike in many other target
-; architechtures, unreachable code being compiled to a trap
@@ -95,57 +92,4 @@ define i32 @missing_ret_noreturn_unreachable() {
; CHECK-NEXT:end_function
call void @ext_never_return()
unreachable
-}
-
-; We could emit no instructions at all for the llvm unreachables in these next
-; three tests, as the signatures match and reach
@@ -85,7 +81,8 @@ define i32 @missing_ret_unreachable() {
}
; This is similar to the above test, but ensures wasm unreachable is emitted
-; even after a noreturn call.
+; even after a noreturn call. Using --no-trap-after-noreturn was previously
+; known to break this.
@@ -95,57 +92,4 @@ define i32 @missing_ret_noreturn_unreachable() {
; CHECK-NEXT:end_function
call void @ext_never_return()
unreachable
-}
-
-; We could emit no instructions at all for the llvm unreachables in these next
-; three tests, as the signatures match and reach
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@@ -1,33 +1,95 @@
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs | FileCheck %s
-; RUN: llc < %s -asm-verbose=false -fast-isel -fast-isel-abort=1
-verify-machineinstrs | FileCheck %s
+; The assertions in this file were autogenerated by
+; utils/update_llc_test_checks.p
https://github.com/aheejin approved this pull request.
Thanks for your patience! Will merge this.
https://github.com/llvm/llvm-project/pull/65876
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Author: Heejin Ahn
Date: 2023-08-31T17:22:44-07:00
New Revision: ef8121b109ef0be9fe94289acbfb9736d66cff15
URL:
https://github.com/llvm/llvm-project/commit/ef8121b109ef0be9fe94289acbfb9736d66cff15
DIFF:
https://github.com/llvm/llvm-project/commit/ef8121b109ef0be9fe94289acbfb9736d66cff15.diff
LO
Author: Heejin Ahn
Date: 2023-09-05T13:29:02-07:00
New Revision: 666098c5b3ea6e01ffe9e827064c26dfaaf9c655
URL:
https://github.com/llvm/llvm-project/commit/666098c5b3ea6e01ffe9e827064c26dfaaf9c655
DIFF:
https://github.com/llvm/llvm-project/commit/666098c5b3ea6e01ffe9e827064c26dfaaf9c655.diff
LO
Author: Heejin Ahn
Date: 2019-10-31T19:52:41-07:00
New Revision: b9903ec8979fc43f1484e1ee8749c7d18ce90bf0
URL:
https://github.com/llvm/llvm-project/commit/b9903ec8979fc43f1484e1ee8749c7d18ce90bf0
DIFF:
https://github.com/llvm/llvm-project/commit/b9903ec8979fc43f1484e1ee8749c7d18ce90bf0.diff
LO
Author: Heejin Ahn
Date: 2019-11-13T19:44:11-08:00
New Revision: 70ee430c6e45c955051bb6b4437c2d1cad8fecb1
URL:
https://github.com/llvm/llvm-project/commit/70ee430c6e45c955051bb6b4437c2d1cad8fecb1
DIFF:
https://github.com/llvm/llvm-project/commit/70ee430c6e45c955051bb6b4437c2d1cad8fecb1.diff
LO
Author: Heejin Ahn
Date: 2020-01-24T14:26:27-08:00
New Revision: 764f4089e89e4693b7bb8f1ee18080703ce760dd
URL:
https://github.com/llvm/llvm-project/commit/764f4089e89e4693b7bb8f1ee18080703ce760dd
DIFF:
https://github.com/llvm/llvm-project/commit/764f4089e89e4693b7bb8f1ee18080703ce760dd.diff
LO
Author: Heejin Ahn
Date: 2020-01-24T14:27:35-08:00
New Revision: 65eb11306e921bb0299100dfc61e79858f903c1b
URL:
https://github.com/llvm/llvm-project/commit/65eb11306e921bb0299100dfc61e79858f903c1b
DIFF:
https://github.com/llvm/llvm-project/commit/65eb11306e921bb0299100dfc61e79858f903c1b.diff
LO
Author: aheejin
Date: Thu Jun 29 17:44:01 2017
New Revision: 306775
URL: http://llvm.org/viewvc/llvm-project?rev=306775&view=rev
Log:
[WebAssembly] Add throw/rethrow builtins for exception handling
Summary:
Add new builtins for throw/rethrow instructions. This follows exception handling
handling
https://github.com/aheejin updated
https://github.com/llvm/llvm-project/pull/80923
>From d6fd48794112d6c140024d7cd55b5fe5e55e Mon Sep 17 00:00:00 2001
From: Heejin Ahn
Date: Tue, 6 Feb 2024 00:31:59 +
Subject: [PATCH 1/2] [WebAssembly] Add more features to generic CPU config
This enabl
@@ -259,6 +259,10 @@ AIX Support
WebAssembly Support
^^^
+The -mcpu=generic configuration now enables nontrapping-fptoint, multivalue,
+reference-types, and bulk-memory.These proposals are standardized and available
+in all major engines.
aheej
https://github.com/aheejin updated
https://github.com/llvm/llvm-project/pull/80923
>From d6fd48794112d6c140024d7cd55b5fe5e55e Mon Sep 17 00:00:00 2001
From: Heejin Ahn
Date: Tue, 6 Feb 2024 00:31:59 +
Subject: [PATCH 1/2] [WebAssembly] Add more features to generic CPU config
This enabl
https://github.com/aheejin updated
https://github.com/llvm/llvm-project/pull/80923
>From d6fd48794112d6c140024d7cd55b5fe5e55e Mon Sep 17 00:00:00 2001
From: Heejin Ahn
Date: Tue, 6 Feb 2024 00:31:59 +
Subject: [PATCH 1/2] [WebAssembly] Add more features to generic CPU config
This enabl
aheejin wrote:
Given that the node version in Chromium CI has been updated successfully
(https://chromium-review.googlesource.com/c/emscripten-releases/+/5503423), I'm
gonna land this.
https://github.com/llvm/llvm-project/pull/93261
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https://github.com/aheejin commented:
Now you have commit access!
https://github.com/llvm/llvm-project/pull/93360
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https://github.com/aheejin edited
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@@ -1199,6 +1213,7 @@ def : Pat<(v2f64 (froundeven (v2f64 V128:$src))),
(NEAREST_F64x2 V128:$src)>;
multiclass SIMDBinaryFP
baseInst> {
defm "" : SIMDBinary;
defm "" : SIMDBinary;
+ defm "" : SIMDBinary;
aheejin wrote:
I understand why it's added, and I
@@ -152,6 +153,18 @@ def F64x2 : Vec {
let prefix = "f64x2";
}
+def F16x8 : Vec {
+ let vt = v8f16;
+ let int_vt = v8i16;
+ let lane_vt = f32;
+ let lane_rc = F32;
+ let lane_bits = 16;
+ let lane_idx = LaneIdx8;
+ let lane_load = int_wasm_loadf16_f32;
+ let splat = PatFrag<
https://github.com/aheejin approved this pull request.
https://github.com/llvm/llvm-project/pull/93360
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aheejin wrote:
This first tried to enable four features (reference-types, multivalue,
bulk-memory, and nontrapping-fptoint), but I think now we can enable the two
first: reference-types and multivalue. These two were actually the first
motivation I started this (these are necessary for the new
https://github.com/aheejin updated
https://github.com/llvm/llvm-project/pull/80923
>From d6fd48794112d6c140024d7cd55b5fe5e55e Mon Sep 17 00:00:00 2001
From: Heejin Ahn
Date: Tue, 6 Feb 2024 00:31:59 +
Subject: [PATCH 1/3] [WebAssembly] Add more features to generic CPU config
This enabl
https://github.com/aheejin edited
https://github.com/llvm/llvm-project/pull/80923
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aheejin wrote:
cc @kripken too (You don't show up in the reviewers list, so I couldn't add you)
https://github.com/llvm/llvm-project/pull/80923
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https://github.com/aheejin updated
https://github.com/llvm/llvm-project/pull/80923
>From d6fd48794112d6c140024d7cd55b5fe5e55e Mon Sep 17 00:00:00 2001
From: Heejin Ahn
Date: Tue, 6 Feb 2024 00:31:59 +
Subject: [PATCH 1/4] [WebAssembly] Add more features to generic CPU config
This enabl
https://github.com/aheejin approved this pull request.
https://github.com/llvm/llvm-project/pull/99388
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@@ -702,6 +702,19 @@ defm "" : ReplaceLane;
defm "" : ReplaceLane;
defm "" : ReplaceLane;
+// For now use an instrinsic for f16x8.replace_lane instead of ReplaceLane
above
+// since LL generated with half type arguments is not well supported and
creates
ahee
https://github.com/aheejin created
https://github.com/llvm/llvm-project/pull/89777
We are currently using `PREFIX-DAG` and `PREFIX-NOT` within a single `PREFIX`
test in a mixed way, but `-DAG` and `-NOT` do not work that way. For example:
Result:
```
1
2
3
```
Test file:
```c
// CHECK-DAG: 3
https://github.com/aheejin created
https://github.com/llvm/llvm-project/pull/89778
This tidies up `wasm-target-features.c` cosmetically:
- Sorts the feature tests alphabetically
- Adds a space after colons
>From 0d0a07ee86159ca3b706a1d17506b531e45c57d6 Mon Sep 17 00:00:00 2001
From: Heejin Ahn
https://github.com/aheejin closed
https://github.com/llvm/llvm-project/pull/89777
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https://github.com/aheejin closed
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https://github.com/aheejin updated
https://github.com/llvm/llvm-project/pull/80923
>From d6fd48794112d6c140024d7cd55b5fe5e55e Mon Sep 17 00:00:00 2001
From: Heejin Ahn
Date: Tue, 6 Feb 2024 00:31:59 +
Subject: [PATCH 1/5] [WebAssembly] Add more features to generic CPU config
This enabl
https://github.com/aheejin updated
https://github.com/llvm/llvm-project/pull/80923
>From d6fd48794112d6c140024d7cd55b5fe5e55e Mon Sep 17 00:00:00 2001
From: Heejin Ahn
Date: Tue, 6 Feb 2024 00:31:59 +
Subject: [PATCH 1/5] [WebAssembly] Add more features to generic CPU config
This enabl
https://github.com/aheejin edited
https://github.com/llvm/llvm-project/pull/80923
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https://github.com/aheejin edited
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https://github.com/aheejin closed
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https://github.com/aheejin created
https://github.com/llvm/llvm-project/pull/90528
This adds the preprocessor define for the half-precision feature and also adds
preprocessor tests.
>From 036d8a7486eab8ee2b434826c6ad5807daba2574 Mon Sep 17 00:00:00 2001
From: Heejin Ahn
Date: Mon, 29 Apr 2024
aheejin wrote:
cc @brendandahl (I couldn't add you as a reviewer because you didn't pop up in
the reviewers list)
Also, this just adds the preprocessor directive, but I'm wondering whether you
really meant to add this to bleeding-edge:
https://github.com/llvm/llvm-project/commit/d9fd0ddef38bb
aheejin wrote:
Looks good to me, but I'm not an expert here.. Maybe @tlively can take a look?
https://github.com/llvm/llvm-project/pull/106465
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https://github.com/aheejin closed
https://github.com/llvm/llvm-project/pull/90528
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https://github.com/aheejin created
https://github.com/llvm/llvm-project/pull/90777
None
>From b9fd03c2740fe924c0ea49bb78c9898412364105 Mon Sep 17 00:00:00 2001
From: Heejin Ahn
Date: Mon, 29 Apr 2024 22:16:46 +
Subject: [PATCH] [WebAssembly] Sort target features (NFC)
---
clang/include/c
https://github.com/aheejin updated
https://github.com/llvm/llvm-project/pull/90777
>From b9fd03c2740fe924c0ea49bb78c9898412364105 Mon Sep 17 00:00:00 2001
From: Heejin Ahn
Date: Mon, 29 Apr 2024 22:16:46 +
Subject: [PATCH 1/2] [WebAssembly] Sort target features (NFC)
---
clang/include/cla
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