quic-garvgupt wrote:
Hi @topperc, can you add instruction alias for cflush and cdiscard instructions
when the rs1 is X0 to `sf.cflush.d.l1` and `sf.cflush.d.l1` respectively, as
this register is optional according to spec?
https://github.com/llvm/llvm-project/pull/83896
_
quic-garvgupt wrote:
Also, I think we might need to update the extensions in the
`RISCVProcessors.td` file under SIFIVE_S76 microcontroller?
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quic-garvgupt wrote:
> > Hi @topperc, can you add instruction alias for cflush and cdiscard
> > instructions when the rs1 is X0 to `sf.cflush.d.l1` and `sf.cflush.d.l1`
> > respectively, as this register is optional according to spec?
>
> x0 has special meaning, but the spec never says it is "
quic-garvgupt wrote:
> > Also, I think we might need to update the extensions in the
> > `RISCVProcessors.td` file under SIFIVE_S76 microcontroller?
>
> This is a M-mode only extension, and we haven't historically been adding M or
> S mode extensions to the -mcpu lists. Except for `xiangshan-n
quic-garvgupt wrote:
Thanks for clearing the confusion around whether rs1 would be optional or not.
Can we also add lit tests for the aliases?
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quic-garvgupt wrote:
Thanks for the prompt reply and latest patchset.
1. Do we need to add documentation in RISCVUsage.rst file for xsfcease?
2. Also, as we are adding cease instruction in this PR, can we rename the PR to
include the cease instruction as well?
https://github.com/llvm/llvm-proj
quic-garvgupt wrote:
I believe the patch is ready to be merged now, but since I am not the reviewer
here, someone else must approve it as well.
Thanks again for the patch!
https://github.com/llvm/llvm-project/pull/83896
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quic-garvgupt wrote:
ping! for merging this PR
https://github.com/llvm/llvm-project/pull/81727
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https://github.com/quic-garvgupt created
https://github.com/llvm/llvm-project/pull/81727
The below culprit patch enabled the generation of asynchronous unwind tables
(-funwind-tables=2) by default for RISCV for both linux and RISCVToolChain
baremetal object. However, since there are 2 baremeta
quic-garvgupt wrote:
Hi
@jonathonpenix @apazos @kito-cheng @asb @MaskRay - Requesting for adding as
reviewers to review the PR. Thanks in advance!
https://github.com/llvm/llvm-project/pull/81727
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quic-garvgupt wrote:
Hi @asb, since Petr already gave a good-ahead to this patch in the meeting, let
me know if we can merge this PR if there are no new changes need to be made
https://github.com/llvm/llvm-project/pull/81727
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https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/81727
>From 42211bccd8ffc60751234ab5695be135ea8b6373 Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Wed, 14 Feb 2024 03:00:20 -0800
Subject: [PATCH 1/2] [RISCV] Disable generation of asynchronous unwind tables
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/81727
>From 42211bccd8ffc60751234ab5695be135ea8b6373 Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Wed, 14 Feb 2024 03:00:20 -0800
Subject: [PATCH] [RISCV] Disable generation of asynchronous unwind tables for
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/81727
>From 8cc7535ed4c05d4cf14cdedc26077eccf06c8d53 Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Wed, 14 Feb 2024 03:00:20 -0800
Subject: [PATCH] [RISCV] Disable generation of asynchronous unwind tables for
@@ -421,3 +421,11 @@
// MIPSN32R6EL: "-target-cpu" "mips64r6"
// MIPSN32R6EL: "-target-abi" "n32"
// MIPSN32R6EL: "-mfloat-abi" "hard"
+
+// RUN: %clang --target=riscv32-unknown-elf --gcc-toolchain="" -### %s 2>&1 |
FileCheck %s -check-prefix=NOUWTABLE
quic-ga
quic-garvgupt wrote:
Hi @asb, I do not have write access, requesting to merge this PR on my behalf.
Also, requesting to backport this PR onto the release branch. Thanks in
advance!
https://github.com/llvm/llvm-project/pull/81727
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https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/81727
>From 0d1f9be389a41ba2f1531bf13e8d1f14aadf9eeb Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Wed, 14 Feb 2024 03:00:20 -0800
Subject: [PATCH] [RISCV] Disable generation of asynchronous unwind tables for
quic-garvgupt wrote:
Hi @MaskRay, please review the updated changes and if they are fine, please
merge this PR on my behalf. Thanks!
https://github.com/llvm/llvm-project/pull/81727
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https://github.com/quic-garvgupt created
https://github.com/llvm/llvm-project/pull/118809
Currently, LLVM has two RISC-V toolchain classes in Clang for baremetal
development, creating unnecessary maintenance overhead. This patch extends the
BareMetal toolchain to support an existing GCC instal
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/118809
>From b74795d44846b79252bd3fb1f1e8179311725c74 Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Wed, 13 Nov 2024 02:45:51 -0800
Subject: [PATCH] [RISCV] Merging RISCVToolChain and BareMetal toolchains
Cu
@@ -503,12 +624,22 @@ void baremetal::Linker::ConstructJob(Compilation &C,
const JobAction &JA,
const llvm::Triple::ArchType Arch = TC.getArch();
const llvm::Triple &Triple = getToolChain().getEffectiveTriple();
- AddLinkerInputs(TC, Inputs, Args, CmdArgs, JA);
+ if (!D
https://github.com/quic-garvgupt created
https://github.com/llvm/llvm-project/pull/121829
This patch introduces the baretmetal toolchain object about GCC Installation.
Currently, if `--gcc-installation` ot `--gcc-install-dir` options are passed on
commandline, then sysroot will be formed from th
quic-garvgupt wrote:
* **#121829** https://app.graphite.dev/github/pr/llvm/llvm-project/121829?utm_source=stack-comment-icon";
target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite"
width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-projec
https://github.com/quic-garvgupt created
https://github.com/llvm/llvm-project/pull/121821
This patch introduces the baretmetal toolchain object about GCC Installation.
Currently, if `--gcc-installation` ot `--gcc-install-dir` options are passed on
commandline, then sysroot will be formed from
https://github.com/quic-garvgupt closed
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https://github.com/llvm/llvm-project/pull/121829
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>From 02d70a2c1fa746eafa87308f0c8109bb2c91164f Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Fri, 13 Dec 2024 05:31:56 -0800
Subject: [PATCH] [RISCV] Teach Barmetal toolchain about GCC installation(1/3
quic-garvgupt wrote:
Hi @petrhosek, following up on our last RISC-V embedded sync-up, can you please
review this patch? Thanks
https://github.com/llvm/llvm-project/pull/121829
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https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/118809
>From 569feb86c654be044781aa5968907a72ea882e88 Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Wed, 13 Nov 2024 02:45:51 -0800
Subject: [PATCH] [WIP] Merging RISCVToolChain and BareMetal toolchains
Curr
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/118809
>From b58f9dd197c78b1e39676022a421ca0e6d5552a5 Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Wed, 13 Nov 2024 02:45:51 -0800
Subject: [PATCH] [WIP] Merging RISCVToolChain and BareMetal toolchains
Curr
@@ -6521,11 +6521,7 @@ const ToolChain &Driver::getToolChain(const ArgList
&Args,
break;
case llvm::Triple::riscv32:
case llvm::Triple::riscv64:
-if (toolchains::RISCVToolChain::hasGCCToolchain(*this, Args))
- TC =
- std::make_
@@ -110,20 +111,95 @@ static std::string computeBaseSysRoot(const Driver &D,
bool IncludeTriple) {
return std::string(SysRootDir);
}
+// GCC sysroot here means form sysroot from either --gcc-install-dir, or from
+// --gcc-toolchain or if the toolchain is installed alongside
@@ -78,8 +86,9 @@ class LLVM_LIBRARY_VISIBILITY BareMetal : public ToolChain {
using OrderedMultilibs =
llvm::iterator_range::const_reverse_iterator>;
OrderedMultilibs getOrderedMultilibs() const;
-
+ bool UseLD;
quic-garvgupt wrote:
please see my
@@ -110,20 +111,93 @@ static std::string computeBaseSysRoot(const Driver &D,
bool IncludeTriple) {
return std::string(SysRootDir);
}
+// GCC sysroot here means form sysroot from either --gcc-install-dir, or from
+// --gcc-toolchain or if the toolchain is installed alongside
quic-garvgupt wrote:
Gentle Ping again!
https://github.com/llvm/llvm-project/pull/121829
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quic-garvgupt wrote:
Gentle Ping!
https://github.com/llvm/llvm-project/pull/121829
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https://github.com/quic-garvgupt edited
https://github.com/llvm/llvm-project/pull/121829
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quic-garvgupt wrote:
I have divided this PR into three separate PRs to streamline the review process
and ensured that ARM and RISCV tests are not modified in the same PR. Please
review them and provide any feedback or comments. Thanks!
[RISCV] Teach Barmetal toolchain about GCC installation(1/
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/121829
>From 03b91a8d408bacec17391b995611dbbb0ea62edd Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Fri, 13 Dec 2024 05:31:56 -0800
Subject: [PATCH] [RISCV] Teach Barmetal toolchain about GCC installation(1/3
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/121829
>From e07a4cd4e0ff77f74b66695923bc998904c14746 Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Fri, 13 Dec 2024 05:31:56 -0800
Subject: [PATCH] [Driver] Teach Barmetal toolchain about GCC installation
T
https://github.com/quic-garvgupt edited
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@@ -110,20 +110,76 @@ static std::string computeBaseSysRoot(const Driver &D,
bool IncludeTriple) {
return std::string(SysRootDir);
}
+std::string BareMetal::computeSysRoot() const {
+ if (!SysRoot.empty())
+return SysRoot;
+
+ std::string SysRoot = getDriver().SysRoot
@@ -79,7 +87,6 @@ class LLVM_LIBRARY_VISIBILITY BareMetal : public ToolChain {
OrderedMultilibs getOrderedMultilibs() const;
std::string SysRoot;
quic-garvgupt wrote:
Removing this private variable was making the code messy because there have
been update
quic-garvgupt wrote:
> I'm looking at this patch in isolation, so its possible that the comments
> here are addressed elasewhere.
>
> It looks like useful functionality to add to the bare metal driver.
>
> It also looks like there is some scope for some documentation, for users and
> for tool
@@ -110,20 +110,81 @@ static std::string computeBaseSysRoot(const Driver &D,
bool IncludeTriple) {
return std::string(SysRootDir);
}
+static bool hasGCCToolChainAlongSideClang(const Driver &D) {
+ SmallString<128> GCCDir;
+ llvm::sys::path::append(GCCDir, D.Dir, "..", D.g
quic-garvgupt wrote:
Hi @petrhosek, I've addressed all your comments. Please review the changes and
approve the PR if everything looks good.
https://github.com/llvm/llvm-project/pull/121829
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>From 9bb78235d2ba008dc49dc4746edbd9978a92396b Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Fri, 13 Dec 2024 05:31:56 -0800
Subject: [PATCH] [RISCV] Teach Barmetal toolchain about GCC installation(1/3
quic-garvgupt wrote:
It's been a few weeks since this patch was last reviewed. If everything looks
good, could someone please provide an LGTM? I'd like to merge this patch soon.
https://github.com/llvm/llvm-project/pull/121829
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@@ -110,20 +111,93 @@ static std::string computeBaseSysRoot(const Driver &D,
bool IncludeTriple) {
return std::string(SysRootDir);
}
+// GCC sysroot here means form sysroot from either --gcc-install-dir, or from
+// --gcc-toolchain or if the toolchain is installed alongside
https://github.com/quic-garvgupt edited
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quic-garvgupt wrote:
Hi @petrhosek, I've addressed all your comments. Please review the changes and
approve the PR if everything looks good.
https://github.com/llvm/llvm-project/pull/121829
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>From 1d0db96afab52903a267d600cab02c24900101af Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Fri, 13 Dec 2024 05:31:56 -0800
Subject: [PATCH] [Driver] Teach Barmetal toolchain about GCC installation
T
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/144649
>From 14a2bb5dead7fa0e3d442e04ba73ad5f98d2e90e Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Tue, 17 Jun 2025 22:49:55 +0530
Subject: [PATCH] [Driver] Add support for crtbegin.o, crtend.o and libgloss
https://github.com/quic-garvgupt closed
https://github.com/llvm/llvm-project/pull/118809
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https://github.com/quic-garvgupt created
https://github.com/llvm/llvm-project/pull/146291
The linker job in BareMetal toolchain object will be used by GNU ld and lld
both.
However, gnuld process the arguments in the order in which they appear on
command
line, whereas there is no such restricti
https://github.com/quic-garvgupt closed
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https://github.com/llvm/llvm-project/pull/147589
>From 6f96fc844751a95ee18b69ddb850ddd2fe76a89c Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Tue, 8 Jul 2025 07:21:37 -0700
Subject: [PATCH 1/2] Propogate appropriate linker flags for `-static-pie` in
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/146849
>From 3d0220ecce368a481981c414f789d9dbbfc49c81 Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Thu, 3 Jul 2025 02:56:01 -0700
Subject: [PATCH] [Driver][RISCV] Fix and print appropriate compiler-rt path
@@ -206,6 +206,15 @@ std::string BareMetal::computeSysRoot() const {
return computeClangRuntimesSysRoot(D, /*IncludeTriple*/ true);
}
+std::string BareMetal::getCompilerRTPath() const {
+ if (IsGCCInstallationValid || detectGCCToolchainAdjacent(getDriver())) {
+SmallStr
https://github.com/quic-garvgupt closed
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>From c6420bc64c2745c49400408ba93afa34eea194e3 Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Tue, 8 Jul 2025 12:44:44 -0700
Subject: [PATCH] Propogate linker flags when `-static-pie` is enabled in
Bar
https://github.com/quic-garvgupt edited
https://github.com/llvm/llvm-project/pull/147589
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>From a1f3797d0acb93e66959c5163aeb49213d2d32a1 Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Tue, 8 Jul 2025 12:44:44 -0700
Subject: [PATCH] Propogate linker flags when `-static-pie` is enabled in
Bar
https://github.com/quic-garvgupt created
https://github.com/llvm/llvm-project/pull/147589
None
>From 6f96fc844751a95ee18b69ddb850ddd2fe76a89c Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Tue, 8 Jul 2025 07:21:37 -0700
Subject: [PATCH 1/2] Propogate appropriate linker flags for `-static-pi
@@ -599,11 +599,18 @@ void baremetal::Linker::ConstructJob(Compilation &C,
const JobAction &JA,
const Driver &D = getToolChain().getDriver();
const llvm::Triple::ArchType Arch = TC.getArch();
const llvm::Triple &Triple = getToolChain().getEffectiveTriple();
+ const bool
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https://github.com/quic-garvgupt created
https://github.com/llvm/llvm-project/pull/146849
Baremetal and RISCVToolchain used different paths for clangrt builtins
relative to resource-dir before RISCVToolChain got removed in commit f8cb798
This created a discrepancy in behavior for riscv target wh
https://github.com/quic-garvgupt edited
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>From 9d48ea76ef90ac9e76ade4af77667e44652e3408 Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Fri, 4 Apr 2025 12:51:19 -0700
Subject: [PATCH] [RISCV][Driver] Add support for `-m` flag to linker job of
quic-garvgupt wrote:
> > Moreover, this patch makes gnuld the default linker for baremetal
> > toolchain object. User need to pass -fuse-ld=lld explicitly to driver to
> > select
> > lld
>
> This seems like an unrelated change, it was not mentioned in the RFC, and it
> breaks things: baremetal
@@ -59,3 +118,39 @@
// CXX-AARCH64-BAREMETAL-NOSYSROOT-LIBCXX: "-internal-isystem"
"{{.*}}/Inputs/basic_aarch64_gcc_tree/lib/gcc/aarch64-none-elf/8.2.1/../../../../aarch64-none-elf/include/c++/v1"
// CXX-AARCH64-BAREMETAL-NOSYSROOT-LIBCXX: "-internal-isystem"
"{{.*}}/Inputs/
https://github.com/quic-garvgupt created
https://github.com/llvm/llvm-project/pull/146304
Add support for `-u` option to force defined symbols. This option is supported
by both lld and gnuld.
This is done as a part of the effort to merge RISCVToolchain object into
BareMetal toolchain object.
@@ -599,11 +599,18 @@ void baremetal::Linker::ConstructJob(Compilation &C,
const JobAction &JA,
const Driver &D = getToolChain().getDriver();
const llvm::Triple::ArchType Arch = TC.getArch();
const llvm::Triple &Triple = getToolChain().getEffectiveTriple();
+ const bool
quic-garvgupt wrote:
>I don't think that this should necessarily prevent this patch from landing. To
>some degree users can just not use the option if the toolchain doesn't support
>it.
The file names for crt files are borrowed from their linux equivalent. However
as already pointed out, if
https://github.com/quic-garvgupt created
https://github.com/llvm/llvm-project/pull/148855
Commit 597ee88 moved the -X flag to a new position in the baremetal toolchain's
linker job,
but unintentionally left the original instance in place.
This patch removes the redundant flag, ensuring -X is
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/147804
>From d92b98015db0e03d1f71658884cd931162835184 Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Wed, 9 Jul 2025 11:58:19 -0700
Subject: [PATCH] Fix adding support for -X flag in Baremetal toolchain
Commi
@@ -613,8 +613,8 @@ void baremetal::Linker::ConstructJob(Compilation &C, const
JobAction &JA,
return;
}
+ CmdArgs.push_back("-X");
quic-garvgupt wrote:
I made a few mistakes in the commit message and title. The intent of this PR is
to add support for
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/145390
>From 296df79cb9e9696daa926267c8a9a853930fdc46 Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Tue, 17 Jun 2025 21:43:17 +0530
Subject: [PATCH] Reland [Driver] Add support for GCC installation detection
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/144649
>From 36f8e160dfad059fdada0a00b5cdc20dde0076c0 Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Tue, 17 Jun 2025 22:49:55 +0530
Subject: [PATCH] [Driver] Add support for crtbegin.o, crtend.o and libgloss
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/121831
>From b9e1db372117d9d418d0812a09874526e88efad4 Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Mon, 6 Jan 2025 10:05:08 -0800
Subject: [PATCH] [RISCV] Integrate RISCV target in baremetal toolchain object
@@ -336,6 +336,26 @@ BareMetal::OrderedMultilibs
BareMetal::getOrderedMultilibs() const {
return llvm::reverse(Default);
}
+ToolChain::CXXStdlibType BareMetal::GetDefaultCXXStdlibType() const {
+ if (getTriple().isRISCV() && GCCInstallation.isValid())
+return ToolChain
@@ -336,6 +336,26 @@ BareMetal::OrderedMultilibs
BareMetal::getOrderedMultilibs() const {
return llvm::reverse(Default);
}
+ToolChain::CXXStdlibType BareMetal::GetDefaultCXXStdlibType() const {
+ if (getTriple().isRISCV() && GCCInstallation.isValid())
+return ToolChain
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/132808
>From e302490b6e6350951e75bd68578606aa7909692e Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Mon, 24 Mar 2025 07:04:59 -0700
Subject: [PATCH] [Driver] Forward sysroot from Driver to linker in BareMetal
https://github.com/quic-garvgupt closed
https://github.com/llvm/llvm-project/pull/148855
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quic-garvgupt wrote:
Hi @smithp35, can you pls review the latest changes and approve this PR if
everything looks fine?
https://github.com/llvm/llvm-project/pull/121829
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https://github.com/quic-garvgupt edited
https://github.com/llvm/llvm-project/pull/144640
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quic-garvgupt wrote:
> > Do the fuchsia builders actually produce output on a failure? We seem to
> > just get exit code 1, but no indication of what filecheck had problems with.
>
> They do; here's a link! Let me know if you have an problems with the Web UI;
> I can paste things here if so.
https://github.com/quic-garvgupt created
https://github.com/llvm/llvm-project/pull/144640
This patch introduces enhancements to the Baremetal toolchain to support
GCC toolchain detection.
- If the --gcc-install-dir or --gcc-toolchain options are provided and
point to valid paths, the sysroot is
https://github.com/quic-garvgupt created
https://github.com/llvm/llvm-project/pull/144655
Fuchsia sets CLANG_DEFAULT_UNWINDLIB to libunwind. As a result, when rtlib is
set to libgcc and unwindlib is not explicitly specified, tests using Fuchsia as
the default platform will fail. To address thi
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