[clang] [llvm] [ARM] enable FENV_ACCESS pragma support for hard-float targets (PR #137101)

https://github.com/davemgreen commented: It looks like this is progressing nicely. It's quite a large change and if there are any parts we can pull out and commit separately, that would help. https://github.com/llvm/llvm-project/pull/137101 ___ cfe-co

[clang] [llvm] [ARM] enable FENV_ACCESS pragma support for hard-float targets (PR #137101)

https://github.com/davemgreen edited https://github.com/llvm/llvm-project/pull/137101 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [ARM] enable FENV_ACCESS pragma support for hard-float targets (PR #137101)

davemgreen wrote: I will try and find some time to take a look at this, I haven't managed to yet. Are there any smaller parts we can split away into their own reviews to start moving it forward? https://github.com/llvm/llvm-project/pull/137101 ___ c

[clang] [llvm] [ARM] enable FENV_ACCESS pragma support for hard-float targets (PR #137101)

davemgreen wrote: Am I right that the bits of FPSCR that are read by the instruction are just the rounding mode? Can we add a new register for just those bits, like FPSCR_NZCV. FPSCR_RM would alias with FPSCR but not FPSCR_NZCV. ``` def FPSCR_RM : ARMReg<3, "fpscr_rm"> { let Aliases = [FPS

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