davemgreen wrote:
Rebase and ping - thanks.
https://github.com/llvm/llvm-project/pull/135064
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Rate limit · GitHub
body {
background-color: #f6f8fa;
color: #24292e;
font-family: -apple-system,BlinkMacSystemFont,Segoe
UI,Helvetica,Arial,san
https://github.com/davemgreen commented:
Can you add a release-note that this new CPU has been added?
https://github.com/llvm/llvm-project/pull/139055
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@@ -1262,7 +1262,7 @@ INSTANTIATE_TEST_SUITE_P(
AArch64CPUAliasTestParams::PrintToStringParamName);
// Note: number of CPUs includes aliases.
-static constexpr unsigned NumAArch64CPUArchs = 89;
+static constexpr unsigned NumAArch64CPUArchs = 90;
davemgreen
https://github.com/davemgreen edited
https://github.com/llvm/llvm-project/pull/139055
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https://github.com/davemgreen commented:
Thanks - this looks sensible to me if these are always present on Grace (I'm
not sure how to check that, I will leave for someone else to review). It
currently uses a bit of a mixture of specifying features individually
(FeatureAES and FeatureSVEAES) an
@@ -944,6 +944,15 @@ def ProcessorFeatures {
list Falkor = [HasV8_0aOps, FeatureCRC, FeatureSHA2,
FeatureAES,
FeatureFPARMv8, FeatureNEON,
FeaturePerfMon,
FeatureRDM];
+ list Grace= [HasV9_0aO
=?utf-8?q?Csan=C3=A1d_Hajd=C3=BA?= ,
=?utf-8?q?Csan=C3=A1d_Hajd=C3=BA?=
Message-ID:
In-Reply-To:
https://github.com/davemgreen approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/125688
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=?utf-8?q?Csanád_Hajdú?=
Message-ID:
In-Reply-To:
https://github.com/davemgreen closed
https://github.com/llvm/llvm-project/pull/125688
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@@ -85,6 +85,9 @@ Changes to the AMDGPU Backend
Changes to the ARM Backend
--
+* The `+nosimd` attribute is now fully supported. Previously, this had no
effect when being used with
+AArch32 targets, however this will now disable NEON instructions being
@@ -334,8 +334,8 @@ ARM_CPU_NAME("cortex-r7", ARMV7R, FK_VFPV3_D16_FP16, false,
(ARM::AEK_MP | ARM::AEK_HWDIVARM))
ARM_CPU_NAME("cortex-r8", ARMV7R, FK_VFPV3_D16_FP16, false,
(ARM::AEK_MP | ARM::AEK_HWDIVARM))
-ARM_CPU_NAME("cortex-r52", ARMV8R, FK_NEO
davemgreen wrote:
It probably needs to not happen with -fno-unaligned-access (or +strict-align),
unless the load / store is known to be 16byte aligned. See
https://github.com/llvm/llvm-project/issues/119732 from recently. (Also I guess
they shouldn't work in BE, but I believe that is not suppo
@@ -0,0 +1,31 @@
+// Ensures that when targeting an ARM target with an Asm file, clang
+// collects the features from the FPU. This is critical in the
+// activation of NEON for supported targets. The Cortex-R52 will be
+// used and tested for VFP and NEON Support
+
+// RUN: %clan
@@ -1,93 +1,93 @@
-// Test of the AArch32 values of -mtp=, checking that each one maps to
-// the right target features.
-
-// RUN: %clang --target=armv7-linux -mtp=cp15 -### -S %s 2>&1 | \
-// RUN: FileCheck -check-prefix=ARMv7_THREAD_POINTER-HARD %s
-// ARMv7_THREAD_POINTER-HARD
https://github.com/davemgreen approved this pull request.
Thanks for the cleanup, LGTM.
(You could probably have just submitted this without review, but that is
getting more rare nowadays).
https://github.com/llvm/llvm-project/pull/134359
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davemgreen wrote:
The way we tried to mitigate this in the past was to use
-target=aarch64-arm-none-eabi for our downstream compiler, and have downstream
differences gated on the arm vendor. It can help keep the upstream tests the
same if they use -target=aarch64-unknown-linux-gnu, and have do
@@ -1,93 +1,93 @@
-// Test of the AArch32 values of -mtp=, checking that each one maps to
-// the right target features.
-
-// RUN: %clang --target=armv7-linux -mtp=cp15 -### -S %s 2>&1 | \
-// RUN: FileCheck -check-prefix=ARMv7_THREAD_POINTER-HARD %s
-// ARMv7_THREAD_POINTER-HARD
davemgreen wrote:
I was going to suggest in #130623 that we undid this part of the change and
made it an NFC except for +[no]simd. But after looking at it this morning.. I
wasn't sure. It at least it deserved to be its own change :)
I believe that if it used `if (!ForAS || !Generic)` then it
@@ -288,6 +288,7 @@ StringRef sys::detail::getHostCPUNameForARM(StringRef
ProcCpuinfoContent) {
if (Implementer == "0x4e") { // NVIDIA Corporation
return StringSwitch(Part)
.Case("0x004", "carmel")
+.Case("0x10", "olympus")
davemgreen wro
@@ -872,6 +883,16 @@ def ProcessorFeatures {
list Carmel = [HasV8_2aOps, FeatureNEON, FeatureSHA2,
FeatureAES,
FeatureFullFP16, FeatureCRC, FeatureLSE,
FeatureRAS, FeatureRDM,
FeatureFPARMv8];
+ li
@@ -679,20 +679,18 @@ llvm::ARM::FPUKind arm::getARMTargetFeatures(const Driver
&D,
CPUArgFPUKind != llvm::ARM::FK_INVALID ? CPUArgFPUKind :
ArchArgFPUKind;
(void)llvm::ARM::getFPUFeatures(FPUKind, Features);
} else {
-bool Generic = true;
-if (!ForAS) {
https://github.com/davemgreen edited
https://github.com/llvm/llvm-project/pull/130623
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@@ -38,6 +38,9 @@ Potentially Breaking Changes
- Fix missing diagnostics for uses of declarations when performing typename
access,
such as when performing member access on a '[[deprecated]]' type alias.
(#GH58547)
+- For ARM targets, when using cc1as, the features included
davemgreen wrote:
I didn't believe that the backend supports it properly yet (or was tested
at-all). I'm not sure of the details on why that was deemed OK not to support
it. @sdesmalen-arm and @paulwalker-arm might know more.
https://github.com/llvm/llvm-project/pull/132772
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davemgreen wrote:
It looks like this came from #122280 / #122716. Sorry about the break, it
should have updated the CPU dependencies correctly too.
LGTM
https://github.com/llvm/llvm-project/pull/139212
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https://github.com/davemgreen edited
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@@ -121,7 +121,7 @@ define i32 @test_orr_extract_from_mul_1(i32 %x, i32 %y) {
; CHECK-THUMB-NEXT:orrs r0, r1
; CHECK-THUMB-NEXT:bx lr
entry:
-; CHECk-THUMB: orrs r0, r1
+; CHECK-THUMB: orrs r0, r1
davemgreen wrote:
You can remove this line entirely, th
@@ -22,7 +22,7 @@ define signext i8 @test1(i32 %A) {
; CHECK-V7: @ %bb.0:
; CHECK-V7-NEXT:sbfx r0, r0, #8, #8
; CHECK-V7-NEXT:bx lr
-; CHECk-V7: sbfx r0, r0, #8, #8
+; CHECK-V7: sbfx r0, r0, #8, #8
davemgreen wrote:
Same here.
https://github.com
davemgreen wrote:
These two are failing:
Clang.CodeGen/paren-list-agg-init.cpp
Clang.CodeGenCXX/microsoft-abi-throw.cpp
Can you try and fix them? (or remove them from this review and handle them
separately). The others look OK.
https://github.com/llvm/llvm-project/pull/140373
__
https://github.com/davemgreen updated
https://github.com/llvm/llvm-project/pull/126945
>From 410d78202cac8221048a83ea466b59cb6e78ea87 Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Wed, 12 Feb 2025 14:31:47 +
Subject: [PATCH 1/2] Add missing Neon Types
The AAPCS64 adds a number of vec
davemgreen wrote:
I was discussing with @tmatheson-arm and he said I could take this over. I've
updated this branch (apparently that does work), trying to address the issues
and clean things up a bit. The new types are not longer a keyword, but that
seems to be OK providing we mark them as imp
https://github.com/davemgreen edited
https://github.com/llvm/llvm-project/pull/126945
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Author: David Green
Date: 2025-05-28T12:26:54+01:00
New Revision: 3a42cbd47d3e92b8794378d2a0e8ec7ae81950d7
URL:
https://github.com/llvm/llvm-project/commit/3a42cbd47d3e92b8794378d2a0e8ec7ae81950d7
DIFF:
https://github.com/llvm/llvm-project/commit/3a42cbd47d3e92b8794378d2a0e8ec7ae81950d7.diff
L
https://github.com/davemgreen updated
https://github.com/llvm/llvm-project/pull/126945
>From 5a17166859760dcbc258892be46f7f909c2b00a9 Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Wed, 12 Feb 2025 14:31:47 +
Subject: [PATCH 1/3] Add missing Neon Types
The AAPCS64 adds a number of vec
davemgreen wrote:
> LGTM with one nitpick. I've run this through a fuzzer which tests ABI
> compatibility with GCC and didn't find any problems.
Thanks for the review and the extra testing!
https://github.com/llvm/llvm-project/pull/126945
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https://github.com/davemgreen created
https://github.com/llvm/llvm-project/pull/141841
This is a fix for a completely unrelated patch, that started to cause failures
in the explicit-build.cpp test because the size of the b.pcm and b-not-a.pcm
files became the same. The alignment added by empty
davemgreen wrote:
Patch up in #141850
https://github.com/llvm/llvm-project/pull/126945
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Author: David Green
Date: 2025-05-15T11:51:58+01:00
New Revision: f8f11c541dec9bfc19f80918cf12da71d6ae7b99
URL:
https://github.com/llvm/llvm-project/commit/f8f11c541dec9bfc19f80918cf12da71d6ae7b99
DIFF:
https://github.com/llvm/llvm-project/commit/f8f11c541dec9bfc19f80918cf12da71d6ae7b99.diff
L
https://github.com/davemgreen updated
https://github.com/llvm/llvm-project/pull/135064
>From 9a56ee32712c213b0fa06257bda9c2f31ec44416 Mon Sep 17 00:00:00 2001
From: David Green
Date: Thu, 15 May 2025 20:36:44 +0100
Subject: [PATCH] [AArch64] Change the coercion type of structs with pointer
mem
https://github.com/davemgreen created
https://github.com/llvm/llvm-project/pull/142760
This updates the element types used in the new __Int8x8_t types added in
#126945, mostly to allow C++ name mangling in ItaniumMangling
mangleAArch64VectorBase to work correctly. Char is replaced by SignedCha
@@ -424,21 +424,74 @@ entry:
ret <2 x double> %0
}
-declare <4 x float> @llvm.ceil.v4f32(<4 x float>)
davemgreen wrote:
Yep - they are not necessary any more for intrinsics, since
https://discourse.llvm.org/t/recent-improvements-to-the-ir-parser/77366.
It
https://github.com/davemgreen updated
https://github.com/llvm/llvm-project/pull/141841
>From 2ed4ce494dbabd94f5b60ae13ee1631fe40a0a4e Mon Sep 17 00:00:00 2001
From: David Green
Date: Wed, 28 May 2025 20:39:53 +0100
Subject: [PATCH 1/2] [ASTWriter] Do not write ObjCCategories if empty.
This is
Author: David Green
Date: 2025-06-02T17:29:46+01:00
New Revision: be6fc0092e44c7fa3981639cbfe692c78a5eb418
URL:
https://github.com/llvm/llvm-project/commit/be6fc0092e44c7fa3981639cbfe692c78a5eb418
DIFF:
https://github.com/llvm/llvm-project/commit/be6fc0092e44c7fa3981639cbfe692c78a5eb418.diff
L
https://github.com/davemgreen created
https://github.com/llvm/llvm-project/pull/142557
Now that #141786 handles scalar and neon types, this adds MVE definitions and
legalization for llvm.roundeven intrinsics. The existing llvm.arm.mve.vrintn
are auto-upgraded to llvm.roundeven like other vrint
https://github.com/davemgreen approved this pull request.
https://github.com/llvm/llvm-project/pull/143570
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Author: David Green
Date: 2025-06-12T20:51:58+01:00
New Revision: 030a471753421477c7ef345cc60091788252fabc
URL:
https://github.com/llvm/llvm-project/commit/030a471753421477c7ef345cc60091788252fabc
DIFF:
https://github.com/llvm/llvm-project/commit/030a471753421477c7ef345cc60091788252fabc.diff
L
davemgreen wrote:
Thanks for the report - I'll put together a fix to exclude address spaces for
the moment.
https://github.com/llvm/llvm-project/pull/135064
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davemgreen wrote:
Ping - thanks
https://github.com/llvm/llvm-project/pull/142760
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davemgreen wrote:
Cheers
https://github.com/llvm/llvm-project/pull/142760
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https://github.com/davemgreen updated
https://github.com/llvm/llvm-project/pull/141841
>From 161981f3aca4ec68f7036f50947281a0ebf9f3f8 Mon Sep 17 00:00:00 2001
From: David Green
Date: Wed, 28 May 2025 20:39:53 +0100
Subject: [PATCH 1/2] [ASTWriter] Do not write ObjCCategories if empty.
This is
davemgreen wrote:
> This change makes sense to me. I have two questions:
>
> 1. Can we add a test that checks that the block is omitted? (maybe via
> `llvm-bcanalyzer -dump`)
> 2. Can we make the `explicit-build.cpp` test more robust? (possibly by
> writing out import signatures)
Thanks - For
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Author: David Green
Date: 2025-06-02T19:30:02+01:00
New Revision: 9f7f4acbf0fc42357e7c804447cb7c2468ca4f4e
URL:
https://github.com/llvm/llvm-project/commit/9f7f4acbf0fc42357e7c804447cb7c2468ca4f4e
DIFF:
https://github.com/llvm/llvm-project/commit/9f7f4acbf0fc42357e7c804447cb7c2468ca4f4e.diff
L
https://github.com/davemgreen created
https://github.com/llvm/llvm-project/pull/142559
This marks ffloor as legal providing that armv8 and neon is present (or
fullfp16 for the fp16 instructions). The existing arm_neon_vrintm intrinsics
are auto-upgraded to llvm.floor.
If this is OK I will upd
https://github.com/davemgreen updated
https://github.com/llvm/llvm-project/pull/135064
>From 6667abfc2191ffca673767c92713f346599f2a35 Mon Sep 17 00:00:00 2001
From: David Green
Date: Thu, 5 Jun 2025 12:01:08 +0100
Subject: [PATCH] [AArch64] Change the coercion type of structs with pointer
memb
davemgreen wrote:
Rebase and ping - it feels like this is a decent compromise for keeping the
code simple.
https://github.com/llvm/llvm-project/pull/135064
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@@ -91,7 +91,9 @@ void fuchsia::Linker::ConstructJob(Compilation &C, const
JobAction &JA,
CmdArgs.push_back("--execute-only");
std::string CPU = getCPUName(D, Args, Triple);
-if (CPU.empty() || CPU == "generic" || CPU == "cortex-a53")
+if (Args.hasFlag(options
https://github.com/davemgreen approved this pull request.
I think this LGTM. I left a comment for maybe having a "IsPossiblyACortexA53"
check that would could reuse in a few places, but that is probably best
extended as a separate issue.
https://github.com/llvm/llvm-project/pull/143915
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davemgreen wrote:
> Personally I'd default to off, particularly after having clang default this
> to off for the last 10 years.
I didn't believe this changed the defaults (I may be mistaken, let me know if I
am!). It was already enabled on Android + Fuchsia, and I believe this patch
keeps tha
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@@ -0,0 +1,723 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc -mtriple=aarch64 -verify-machineinstrs --mattr=+cpa
-aarch64-use-featcpa-codegen=true -O0 -global-isel=1 -global-isel-abort=1 %s -o
- 2>&1 | FileCh
@@ -10716,6 +10716,21 @@ let Predicates = [HasCPA] in {
// Scalar multiply-add/subtract
def MADDPT : MulAccumCPA<0, "maddpt">;
def MSUBPT : MulAccumCPA<1, "msubpt">;
+
+ def : Pat<(ptradd GPR64sp:$Rn, GPR64sp:$Rm),
+(ADDPT_shift GPR64sp:$Rn, GPR64sp:$Rm, (i32
https://github.com/davemgreen commented:
Thanks for the updates, this is quite a bit simpler now. As far as I can tell
this looks OK to me.
https://github.com/llvm/llvm-project/pull/105669
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@@ -0,0 +1,723 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc -mtriple=aarch64 -verify-machineinstrs --mattr=+cpa
-aarch64-use-featcpa-codegen=true -O0 -global-isel=1 -global-isel-abort=1 %s -o
- 2>&1 | FileCh
davemgreen wrote:
> The issue seems to be with pointers to functions, adding
>
> ```
>FDTy = getContext().getBaseElementType(FDTy);
> return (FDTy->isPointerOrReferenceType() &&
> getContext().getTypeSize(FDTy) == 64 &&
> -!FDTy->getPointeeTy
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