https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/110182
>From af1adfafaa09bc7992cf9aaf34a6121cf2d56d5b Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Thu, 26 Sep 2024 04:16:52 +0100
Subject: [PATCH 1/2] Mark globals as `constant` if they have been annotated
with `_
AlexVlx wrote:
I've extende the test under `Transforms/GlobalOpt/externally-initialized.ll` to
also cover `constant`s / ensure they don't get CSEd.
https://github.com/llvm/llvm-project/pull/110182
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https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/110182
>From af1adfafaa09bc7992cf9aaf34a6121cf2d56d5b Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Thu, 26 Sep 2024 04:16:52 +0100
Subject: [PATCH 1/3] Mark globals as `constant` if they have been annotated
with `_
https://github.com/AlexVlx created
https://github.com/llvm/llvm-project/pull/109415
This is primarily meant to address the issue identified in #109182, around
incorrect usage of `-fsycl-is-device`; we now have AMDGCN flavoured SPIR-V
which retains the desired behaviour around the default AS an
https://github.com/AlexVlx edited
https://github.com/llvm/llvm-project/pull/109415
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AlexVlx wrote:
> > Ah, I remember now why the SYCL flag / mode was abused here (the default AS
> > Map for SPIR-V is problematic in this case); I believe that using the
> > `spirv64-amd-amdhsa` triple instead of `spirv64-unknown-unknown` will work,
> > and allow for the removal of the SYCL ref
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/109415
>From 75ca598c7e8a583545f50ee2c526556df261cc7f Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Fri, 20 Sep 2024 13:25:49 +0100
Subject: [PATCH 1/2] Implement `getGlobalVarAddressSpace` for SPIR-V; stop
using SY
@@ -0,0 +1,163 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o -
| FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o -
-filetype=obj | spirv-val %}
+
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unkno
@@ -58,7 +58,35 @@ class SPIRVTargetCodeGenInfo : public
CommonSPIRTargetCodeGenInfo {
SPIRVTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
: CommonSPIRTargetCodeGenInfo(std::make_unique(CGT)) {}
void setCUDAKernelCallingConvention(const FunctionType *&FT) const overri
@@ -1,7 +1,7 @@
; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
--check-prefix=CHECK-SPIRV
; CHECK-SPIRV: %[[#Int:]] = OpTypeInt 32 0
-; CHECK-SPIRV-DAG: %[[#MemScope_Device:]] = OpConstant %[[#Int]] 1
+; CHECK-SPIRV-DAG: %[[#MemScope_AllSvmDevic
@@ -1,56 +0,0 @@
-; This test aims to check ability to support "Arithmetic with Overflow"
intrinsics
AlexVlx wrote:
This relies on `CodeGenPrepare::combineToUSubWithOverflow` firing, however when
encoding the int sizes we can do loop strength reduction before,
@@ -54,14 +54,14 @@ static std::string computeDataLayout(const Triple &TT) {
// memory model used for graphics: PhysicalStorageBuffer64. But it shouldn't
// mean anything.
if (Arch == Triple::spirv32)
-return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
-
https://github.com/AlexVlx created
https://github.com/llvm/llvm-project/pull/110695
SPIR-V doesn't currently encode "native" integer bit-widths in its
datalayout(s). This is problematic as it leads to optimisation passes, such as
InstCombine, getting ideas and e.g. shrinking to non byte-multip
@@ -1,56 +0,0 @@
-; This test aims to check ability to support "Arithmetic with Overflow"
intrinsics
AlexVlx wrote:
Right but it's relying on a non-guaranteed maybe-optimisation firing, as far as
I can tell.
https://github.com/llvm/llvm-project/pull/110695
___
@@ -1,56 +0,0 @@
-; This test aims to check ability to support "Arithmetic with Overflow"
intrinsics
AlexVlx wrote:
Can you please elaborate on "why"? Again, this relies on an opportunistic
optimisation, that is not crucial / can be superseded by others. If the
AlexVlx wrote:
> +1 to @efriedma-quic and @jdoerfert's comments. DataLayout should remain as
> generic as possible. Trying to encode a concept of "_the_ flat address space"
> in it seems way too specific to one optimization for one or two targets.
This isn't purely a nice to have optimisation
AlexVlx wrote:
Instead of removing the test case altogether, does it not suffice to remove
the SYCL reference / SYCL specific flag, which I interpret as the problem being
addressed? SYCL per se is not a target, but rather a language? Apologies if I'm
missing something.
https://github.com/llv
@@ -33,7 +33,8 @@
#include "llvm/Support/Debug.h"
namespace {
AlexVlx wrote:
Done.
https://github.com/llvm/llvm-project/pull/106429
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@@ -251,6 +251,24 @@ SPIRV::MemorySemantics::MemorySemantics
getMemSemantics(AtomicOrdering Ord) {
llvm_unreachable(nullptr);
}
+SPIRV::Scope::Scope getMemScope(const LLVMContext &Ctx, SyncScope::ID ID) {
AlexVlx wrote:
I've taken this suggestion, but type
AlexVlx wrote:
> > > Are there any tests available to check this behavior?
> >
> >
> > The reworked tests do verify / rely on this behaviour, but I can add an
> > individual test for both vanilla and AMDGCN flavoured SPIR-V, if that is
> > preferred (might be better anyway).
>
> Thanks @Alex
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/109415
>From 75ca598c7e8a583545f50ee2c526556df261cc7f Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Fri, 20 Sep 2024 13:25:49 +0100
Subject: [PATCH 1/2] Implement `getGlobalVarAddressSpace` for SPIR-V; stop
using SY
AlexVlx wrote:
I don't think we should rely on these on the host at all, the addition was a
design mistake initially, we probably should not double down on it. The wave
size is an intrinsic property of the target, the host doesn't really have that
property; there are canonical ways of querying
@@ -91,6 +97,88 @@ SPIRVTargetMachine::SPIRVTargetMachine(const Target &T,
const Triple &TT,
setRequiresStructuredCFG(false);
}
+enum AddressSpace {
+ Function = storageClassToAddressSpace(SPIRV::StorageClass::Function),
+ CrossWorkgroup =
+ storageClassToAddressSpac
@@ -178,6 +266,9 @@ void SPIRVPassConfig::addIRPasses() {
addPass(createSPIRVStructurizerPass());
}
+ if (TM.getOptLevel() > CodeGenOptLevel::None)
+addPass(createInferAddressSpacesPass(AddressSpace::Generic));
AlexVlx wrote:
Because if one invokes
@@ -91,6 +97,88 @@ SPIRVTargetMachine::SPIRVTargetMachine(const Target &T,
const Triple &TT,
setRequiresStructuredCFG(false);
}
+enum AddressSpace {
+ Function = storageClassToAddressSpace(SPIRV::StorageClass::Function),
+ CrossWorkgroup =
+ storageClassToAddressSpac
@@ -91,6 +97,88 @@ SPIRVTargetMachine::SPIRVTargetMachine(const Target &T,
const Triple &TT,
setRequiresStructuredCFG(false);
}
+enum AddressSpace {
+ Function = storageClassToAddressSpace(SPIRV::StorageClass::Function),
+ CrossWorkgroup =
+ storageClassToAddressSpac
AlexVlx wrote:
> Let me clarify myself, _BitInt(N) will work with the change, I have no
> doubts. But I can imagine a SPIR-V extension to appear that would add support
> for 4-bit integers. And I can imagine that we would want to not only be able
> to emit 4-bit integers in the frontend, but a
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/114481
>From 3ba88ce598aaab269169f0a5db5981c9a9ac8603 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Thu, 31 Oct 2024 22:38:36 +
Subject: [PATCH 01/10] Add pass to handle AMDGCN pseudo-intrinsics (abstract
placeh
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/114062
>From d2d2d3d5db3f639aab178f9ca9a20db2842d2b65 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 29 Oct 2024 14:20:44 +
Subject: [PATCH 1/8] `sret` args should always point to the `alloca` AS, so we
can
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/113509
>From 4a18bbc256051f30805620f65a4db037ea2fe96c Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Thu, 24 Oct 2024 01:14:28 +0100
Subject: [PATCH 1/3] Add support for mixing AMDGCNSPIRV & concrete
`offload-arch`s.
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/110447
>From f65d933740225122d832a340b89fe4da0d80a204 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Mon, 30 Sep 2024 03:09:58 +0100
Subject: [PATCH] Don't use the OpenCLKernel CC when targeting AMDGCNSPIRV.
---
cla
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/110695
>From 758fb6e28844d89031b5497d651cb2a9b71b6a0e Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 1 Oct 2024 17:10:50 +0100
Subject: [PATCH 1/2] Explicitly encode native integer widths for SPIR-V.
---
clang/
https://github.com/AlexVlx commented:
Gentle ping.
https://github.com/llvm/llvm-project/pull/110447
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https://github.com/llvm/llvm-project/pull/110447
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https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/110695
>From 758fb6e28844d89031b5497d651cb2a9b71b6a0e Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 1 Oct 2024 17:10:50 +0100
Subject: [PATCH 1/2] Explicitly encode native integer widths for SPIR-V.
---
clang/
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/114481
>From 3ba88ce598aaab269169f0a5db5981c9a9ac8603 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Thu, 31 Oct 2024 22:38:36 +
Subject: [PATCH 1/9] Add pass to handle AMDGCN pseudo-intrinsics (abstract
placehol
AlexVlx wrote:
> Don't know how anything was working before. There must have been a recent
> regression, but I haven't looked yet.
I don’t know if we want to do this blindly, it’s generally a good catch for
actual bugs. I assume that this “worked” before because the AS map hack was in
place.
AlexVlx wrote:
> The following also currently crashes with the flags in question:
>
> ```
> void use_of_private_var()
> {
> int x = 0 ;
> __private void* xx = &x;
> }
> ```
>
> And the AST for the call in your testcase looks fine:
>
> ```
> `-CallExpr 0xd4aeec8 'void'
> |-Im
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/114481
>From 3ba88ce598aaab269169f0a5db5981c9a9ac8603 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Thu, 31 Oct 2024 22:38:36 +
Subject: [PATCH 01/10] Add pass to handle AMDGCN pseudo-intrinsics (abstract
placeh
@@ -6,48 +7,78 @@
; RUN: opt -O3 -S < %s | FileCheck -check-prefix=OPT %s
; RUN: opt -mtriple=amdgcn-- -O3 -S < %s | FileCheck -check-prefix=OPT %s
-; RUN: opt -mtriple=amdgcn-- -O3 -mattr=+wavefrontsize32 -S < %s | FileCheck
-check-prefix=OPT %s
-; RUN: opt -mtriple=amdgcn--
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --version 5
AlexVlx wrote:
Done.
https://github.com/llvm/llvm-project/pull/114481
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https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/114481
>From 3ba88ce598aaab269169f0a5db5981c9a9ac8603 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Thu, 31 Oct 2024 22:38:36 +
Subject: [PATCH 01/10] Add pass to handle AMDGCN pseudo-intrinsics (abstract
placeh
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/114481
>From 3ba88ce598aaab269169f0a5db5981c9a9ac8603 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Thu, 31 Oct 2024 22:38:36 +
Subject: [PATCH 01/10] Add pass to handle AMDGCN pseudo-intrinsics (abstract
placeh
@@ -1780,6 +1780,14 @@ class TargetInfo : public TransferrableTargetInfo,
return 0;
}
+ /// \returns Target specific address space for indirect (e.g. sret)
arguments.
+ /// If such an address space exists, it must be convertible to and from the
+ /// alloca address s
https://github.com/AlexVlx approved this pull request.
LGTM, thanks.
https://github.com/llvm/llvm-project/pull/112849
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https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/114062
>From d2d2d3d5db3f639aab178f9ca9a20db2842d2b65 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 29 Oct 2024 14:20:44 +
Subject: [PATCH 01/11] `sret` args should always point to the `alloca` AS, so
we ca
@@ -5158,14 +5155,17 @@ RValue CodeGenFunction::EmitCall(const CGFunctionInfo
&CallInfo,
} else if (!ReturnValue.isNull()) {
SRetPtr = ReturnValue.getAddress();
} else {
- SRetPtr = CreateMemTemp(RetTy, "tmp", &SRetAlloca);
+ SRetPtr = CreateMemTempWith
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/114481
>From 3ba88ce598aaab269169f0a5db5981c9a9ac8603 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Thu, 31 Oct 2024 22:38:36 +
Subject: [PATCH 01/11] Add pass to handle AMDGCN pseudo-intrinsics (abstract
placeh
https://github.com/AlexVlx closed
https://github.com/llvm/llvm-project/pull/114481
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AlexVlx wrote:
Thank you for this, unfortunately I don't quite see the reason for adding
another twiddly bit here. We are long term migrating away from the
default-is-private hack, and to get the benefits you are looking for you can
simply compile for CL2, or enable the generic as extension, f
https://github.com/AlexVlx requested changes to this pull request.
In principle I am against this, it adds a relatively brittle hook, and bypasses
the pre-existing mechanisms (use CL2 or enable the generic-as extension) for
obtaining this behaviour, in a way that does not ensure that the pre-ex
https://github.com/AlexVlx closed
https://github.com/llvm/llvm-project/pull/116804
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@@ -0,0 +1,29 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
AlexVlx wrote:
Done.
https://github.com/llvm/llvm-project/pull/110897
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@@ -91,6 +97,100 @@ SPIRVTargetMachine::SPIRVTargetMachine(const Target &T,
const Triple &TT,
setRequiresStructuredCFG(false);
}
+enum AddressSpace {
+ Function = storageClassToAddressSpace(SPIRV::StorageClass::Function),
+ CrossWorkgroup =
+ storageClassToAddressSpa
@@ -91,6 +97,88 @@ SPIRVTargetMachine::SPIRVTargetMachine(const Target &T,
const Triple &TT,
setRequiresStructuredCFG(false);
}
+enum AddressSpace {
+ Function = storageClassToAddressSpace(SPIRV::StorageClass::Function),
+ CrossWorkgroup =
+ storageClassToAddressSpac
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/114481
>From 3ba88ce598aaab269169f0a5db5981c9a9ac8603 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Thu, 31 Oct 2024 22:38:36 +
Subject: [PATCH 01/11] Add pass to handle AMDGCN pseudo-intrinsics (abstract
placeh
https://github.com/AlexVlx edited
https://github.com/llvm/llvm-project/pull/114481
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https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/114481
>From 3ba88ce598aaab269169f0a5db5981c9a9ac8603 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Thu, 31 Oct 2024 22:38:36 +
Subject: [PATCH 01/10] Add pass to handle AMDGCN pseudo-intrinsics (abstract
placeh
@@ -1024,6 +1024,15 @@ GCNTTIImpl::instCombineIntrinsic(InstCombiner &IC,
IntrinsicInst &II) const {
}
break;
}
+ case Intrinsic::amdgcn_wavefrontsize: {
+// TODO: this is a workaround for the pseudo-generic target one gets with
no
+// specified mcpu, which
AlexVlx wrote:
> > > reqd_work_group_size is for OpenCL reqd_work_group_size attribute and it
> > > sets exact block size. amdgpu-flat-work-group-size sets a (min, max)
> > > range for block size.
> > > HIP launch bounds sets a block size range (1, bound). It cannot be
> > > represented by req
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/116804
>From 02a607446bf23781255f401d880b67c705cf11fd Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 19 Nov 2024 13:42:54 +
Subject: [PATCH 1/3] Use `used`'s element type if it's available.
---
llvm/lib/Bit
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/116804
>From 02a607446bf23781255f401d880b67c705cf11fd Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 19 Nov 2024 13:42:54 +
Subject: [PATCH 1/3] Use `used`'s element type if it's available.
---
llvm/lib/Bit
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/116820
>From c5efdd24c0c889e26e3b00865780970ca5ed1f4c Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 19 Nov 2024 14:55:25 +
Subject: [PATCH 1/2] Translate `amdgpu_flat_work_group_size` into
`reqd_work_group_
https://github.com/AlexVlx edited
https://github.com/llvm/llvm-project/pull/116804
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https://github.com/llvm/llvm-project/pull/116804
>From 02a607446bf23781255f401d880b67c705cf11fd Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 19 Nov 2024 13:42:54 +
Subject: [PATCH 1/2] Use `used`'s element type if it's available.
---
llvm/lib/Bit
https://github.com/AlexVlx commented:
> Mind adding a test case? Perhaps something like the embed-bitcode.ll, but
> instead checking the round-tripping of compiler.used ?
Done, although slightly differently; it does reflect that when there is a
pre-existing compiler.used its element type is
https://github.com/AlexVlx created
https://github.com/llvm/llvm-project/pull/116820
HIPAMD relies on the `amdgpu_flat_work_group_size` attribute to implement key
functionality such as the `__launch_bounds__` `__global__` function annotation.
This attribute is not available / directly translata
https://github.com/AlexVlx closed
https://github.com/llvm/llvm-project/pull/116820
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https://github.com/llvm/llvm-project/pull/114062
>From d2d2d3d5db3f639aab178f9ca9a20db2842d2b65 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 29 Oct 2024 14:20:44 +
Subject: [PATCH 01/10] `sret` args should always point to the `alloca` AS, so
we ca
https://github.com/AlexVlx edited
https://github.com/llvm/llvm-project/pull/114062
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https://github.com/llvm/llvm-project/pull/114062
>From d2d2d3d5db3f639aab178f9ca9a20db2842d2b65 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 29 Oct 2024 14:20:44 +
Subject: [PATCH 01/10] `sret` args should always point to the `alloca` AS, so
we ca
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/114062
>From d2d2d3d5db3f639aab178f9ca9a20db2842d2b65 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 29 Oct 2024 14:20:44 +
Subject: [PATCH 1/9] `sret` args should always point to the `alloca` AS, so we
can
@@ -5390,11 +5390,19 @@ RValue CodeGenFunction::EmitCall(const CGFunctionInfo
&CallInfo,
V->getType()->isIntegerTy())
V = Builder.CreateZExt(V, ArgInfo.getCoerceToType());
-// If the argument doesn't match, perform a bitcast to coerce it. This
-
@@ -5159,16 +5156,19 @@ RValue CodeGenFunction::EmitCall(const CGFunctionInfo
&CallInfo,
} else if (!ReturnValue.isNull()) {
SRetPtr = ReturnValue.getAddress();
} else {
- SRetPtr = CreateMemTemp(RetTy, "tmp", &SRetAlloca);
+ SRetPtr = CreateMemTempWith
https://github.com/AlexVlx edited
https://github.com/llvm/llvm-project/pull/114062
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@@ -91,6 +97,88 @@ SPIRVTargetMachine::SPIRVTargetMachine(const Target &T,
const Triple &TT,
setRequiresStructuredCFG(false);
}
+enum AddressSpace {
+ Function = storageClassToAddressSpace(SPIRV::StorageClass::Function),
+ CrossWorkgroup =
+ storageClassToAddressSpac
@@ -5390,11 +5390,19 @@ RValue CodeGenFunction::EmitCall(const CGFunctionInfo
&CallInfo,
V->getType()->isIntegerTy())
V = Builder.CreateZExt(V, ArgInfo.getCoerceToType());
-// If the argument doesn't match, perform a bitcast to coerce it. This
-
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/114481
>From 3ba88ce598aaab269169f0a5db5981c9a9ac8603 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Thu, 31 Oct 2024 22:38:36 +
Subject: [PATCH 01/12] Add pass to handle AMDGCN pseudo-intrinsics (abstract
placeh
https://github.com/AlexVlx commented:
> #117410 gives you a way to do this without explicitly looking at the features
> or CPU
Cheers for this @arsenm, very useful; I've switched over to using it instead.
https://github.com/llvm/llvm-project/pull/114481
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https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/114062
>From d2d2d3d5db3f639aab178f9ca9a20db2842d2b65 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 29 Oct 2024 14:20:44 +
Subject: [PATCH 01/11] `sret` args should always point to the `alloca` AS, so
we ca
@@ -1350,7 +1350,7 @@ bool ItaniumCXXABI::classifyReturnType(CGFunctionInfo
&FI) const {
// If C++ prohibits us from making a copy, return by address.
if (!RD->canPassInRegisters()) {
auto Align = CGM.getContext().getTypeAlignInChars(FI.getReturnType());
-FI.getRet
@@ -92,6 +98,63 @@ SPIRVTargetMachine::SPIRVTargetMachine(const Target &T,
const Triple &TT,
setRequiresStructuredCFG(false);
}
+enum AddressSpace {
+ Function = storageClassToAddressSpace(SPIRV::StorageClass::Function),
+ CrossWorkgroup =
+ storageClassToAddressSpac
@@ -105,6 +105,11 @@ void AMDGPUABIInfo::computeInfo(CGFunctionInfo &FI) const {
if (!getCXXABI().classifyReturnType(FI))
FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
+ // srets / indirect returns are unconditionally in the alloca AS.
+ if (FI.getReturn
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/116820
>From c5efdd24c0c889e26e3b00865780970ca5ed1f4c Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 19 Nov 2024 14:55:25 +
Subject: [PATCH 1/3] Translate `amdgpu_flat_work_group_size` into
`reqd_work_group_
https://github.com/AlexVlx edited
https://github.com/llvm/llvm-project/pull/116820
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https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/116820
>From c5efdd24c0c889e26e3b00865780970ca5ed1f4c Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 19 Nov 2024 14:55:25 +
Subject: [PATCH 1/3] Translate `amdgpu_flat_work_group_size` into
`reqd_work_group_
@@ -21,9 +21,12 @@ ABIArgInfo DefaultABIInfo::classifyArgumentType(QualType Ty)
const {
// Records with non-trivial destructors/copy-constructors should not be
// passed by value.
if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
- return getN
@@ -814,7 +816,10 @@ static ABIArgInfo classifyType(CodeGenModule &CGM,
CanQualType type,
auto &layout = CGM.getContext().getASTRecordLayout(record);
if (mustPassRecordIndirectly(CGM, record))
- return ABIArgInfo::getIndirect(layout.getAlignment(), /*byval*/ fals
AlexVlx wrote:
> `CodeGenHipStdPar/unsupported-builtins.cpp` is pretty interesting actually,
> it looks like it tests for some behavior in CodeGen that seems like it's
> trying to fix the exact same problem
>
> The other two tests seem to be actually unrelated breakages though.
It is not quit
AlexVlx wrote:
> > I don't think it makes any sense for `__has_builtin` to return true when
> > the target does not in-fact have the builtin. Most of the time this is used
> > to guard target specific code, which will then be wrong if it's compiled on
> > the device. Realistically the solution
https://github.com/AlexVlx closed
https://github.com/llvm/llvm-project/pull/116820
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@@ -49,6 +49,8 @@ class ABIInfo {
CodeGen::CodeGenTypes &CGT;
llvm::CallingConv::ID RuntimeCC;
+ unsigned getTargetDefaultAS() const;
AlexVlx wrote:
Sure, but I couldn't quite figure out any other convenient, accessible,
non-intrusive place to stash thi
AlexVlx wrote:
> ping, this really needs to be in the release branch. The device library build
> is broken without this
@rjmccall any additional issues / comments / suggestions / objections?
https://github.com/llvm/llvm-project/pull/114062
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@@ -225,7 +225,9 @@ ABIArgInfo AMDGPUABIInfo::classifyArgumentType(QualType Ty,
bool Variadic,
// Records with non-trivial destructors/copy-constructors should not be
// passed by value.
if (auto RAA = getRecordArgABI(Ty, getCXXABI()))
- return getNaturalAlign
@@ -800,7 +800,9 @@ static ABIArgInfo classifyExpandedType(SwiftAggLowering
&lowering,
if (lowering.empty()) {
return ABIArgInfo::getIgnore();
} else if (lowering.shouldPassIndirectly(forReturn)) {
-return ABIArgInfo::getIndirect(alignmentForIndirect, /*byval*/ fal
AlexVlx wrote:
> I'm fine with how you're handling the address spaces for now.
>
> I'd like to talk about the rule you're implementing, though. It looks like
> it's supposed to be:
>
> * return values always use the alloca AS
> * arguments always use the default AS
> * whether something is ind
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/116820
>From c5efdd24c0c889e26e3b00865780970ca5ed1f4c Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 19 Nov 2024 14:55:25 +
Subject: [PATCH 1/3] Translate `amdgpu_flat_work_group_size` into
`reqd_work_group_
https://github.com/AlexVlx reopened
https://github.com/llvm/llvm-project/pull/116820
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https://github.com/AlexVlx edited
https://github.com/llvm/llvm-project/pull/116820
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