[PATCH] D154567: [RISCV] Use ClangBuiltin in IntrinsicsRISCV.td to map some scalar crypto builtins to IR intrinsic.

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154567/new/ https://reviews.llvm.org/D154567 ___ cfe-

[PATCH] D154577: [RISCV] Use 'long' in sha512 builtin tests. NFC

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154577/new/ https://reviews.llvm.org/D154577 ___ cfe-

[PATCH] D154681: [RISCV] Split __builtin_riscv_xperm4/8 into separate _32 and _64 builtins.

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154681/new/ https://reviews.llvm.org/D154681 ___ cfe-

[PATCH] D154683: [RISCV] Split __builtin_riscv_brev8 into _32 and _64 builtin.

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154683/new/ https://reviews.llvm.org/D154683 ___ cfe-

[PATCH] D149248: [RISCV][MC] MC layer support for the experimental zacas extension

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG29f630a1ddcb: [RISCV][MC] MC layer support for the experimental zacas extension (authored by asb). Changed prior to commit: https://reviews.llvm.o

[PATCH] D125765: [RISCV] Add type aliases float16_t, float32_t and float64_t

asb added a reviewer: eopXD. asb added a comment. Adding eop as a reviewer. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D125765/new/ https://reviews.llvm.org/D125765 ___ cfe-commits mailing list cfe-com

[PATCH] D155339: Enable zba and zbs for RISCV64 Android

asb accepted this revision. asb added a comment. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D155339/new/ https://reviews.llvm.org/D155339 ___ cfe-commits mailing list cfe-commits@lists.llvm.org h

[PATCH] D152279: [Driver] Default -msmall-data-limit= to 0

asb added a comment. In D152279#4612099 , @craig.topper wrote: > In D152279#4612087 , @MaskRay wrote: > >> I am still interested in moving this forward. What should be done here? If >> the decision is to keep th

[PATCH] D119541: [RISCV] Fix RISCVTargetInfo::initFeatureMap, add non-ISA features back after implication

asb added a comment. In D119541#3940597 , @arichardson wrote: > I just noticed that target features (e.g. -mrelax) are broken in all LLVM 14 > releases due to D113336 . This should have > been cherry-picked back tot t

[PATCH] D138810: [RISCV] Support vector crypto extension C intrinsics

asb added a comment. Thanks for sharing these patches. I appreciate you're probably not expecting in-depth reviews at this point, but if you could update the patch description to link to the current spec for these intrinsics it would be a lot easier for anyone who is able to give some early fee

[PATCH] D138930: [RISCV] Add macro to imply compiler availability on RISC-V Vector intrinsics version

asb accepted this revision. asb added a comment. LGTM, thanks! Comment at: clang/lib/Basic/Targets/RISCV.cpp:195 Builder.defineMacro("__riscv_vector"); +// Currently we support the v0.10 RISC-V V intrinsics +unsigned Version = (0 * 100) + (10 * 1000); -

[PATCH] D139025: [NFC][RISCV] Extract utility to calculate value through MajorVersion and MinorVersion

asb added inline comments. Comment at: llvm/include/llvm/Support/RISCVISAInfo.h:25 + unsigned getVersionValue() { +return MajorVersion * 100 + MinorVersion * 1000; + } Would this be better as `return getVersionValue(MajorVersion, MinorVersion);` in ord

[PATCH] D69590: [RISCV] Fix ILP32D lowering for double+double/double+int return types

asb added a comment. Thanks James - won't this still leave problems for structs that need flattening? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D69590/new/ https://reviews.llvm.org/D69590 ___ cfe-co

[PATCH] D69383: [RISCV] Match GCC `-march`/`-mabi` driver defaults

asb accepted this revision. asb added a comment. Please update the commit message to clarify the cases where we do deviate from the GCC defaults, but this looks good to me. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D69383/new/ https://reviews.l

[PATCH] D73891: [RISCV] Support experimental/unratified extensions

asb accepted this revision. asb added a comment. LGTM, thanks Simon! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D73891/new/ https://reviews.llvm.org/D73891 ___ cfe-commits mailing list cfe-commits@li

[PATCH] D44189: [RISCV] Verify the input value of -march=

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. Thanks for this Kito. A tiny formatting nit, but otherwise this looks good to me. Comment at: lib/Driver/ToolChains/Arch/RISCV.cpp:70 + while (StdExtsItr != StdExts.end() &&

[PATCH] D44727: [RISCV] Implement getTargetDefines, handleTargetFeatures and hasFeature for RISCVTargetInfo

asb added subscribers: doug.gregor, rsmith. asb added a comment. Thanks Kito. I've added some comments inline. Nitpicking: the patch description would be more accurate to say it "extends getTargetDefines", as obviously an initial implementation was already present Comment at:

[PATCH] D45237: [RISCV] Fix logic check if frame pointer should be used

asb added a comment. Could you please add a test, perhaps to test/Driver/frame-pointer.c? My understanding is that in general there is a desire for codegen to remain the same or as close as possible whether it's a -g build or not, so I think disabling fp elimination for debug builds wouldn't be

[PATCH] D44727: [RISCV] Extend getTargetDefines for RISCVTargetInfo

asb added a comment. Thanks Eli for the info on hasFeature. I think the only thing now missing is test coverage for the defines. Comment at: lib/Basic/Targets/RISCV.cpp:53-73 + if (HasM) { +Builder.defineMacro("__riscv_mul"); +Builder.defineMacro("__riscv_div"); +

[PATCH] D44727: [RISCV] Extend getTargetDefines for RISCVTargetInfo

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. Thanks, this looks good to me. Comment at: lib/Basic/Targets/RISCV.cpp:62-70 + if (HasD) +Builder.defineMacro("__riscv_flen", "64"); + else if (HasF) +Builder.defineMacro

[PATCH] D45284: [RISCV] More validations on the input value of -march=

asb added inline comments. Comment at: test/Driver/riscv-arch.c:151 +// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-LETTER %s +// RV32-LETTER: error: invalid arch name 'rv32e', +// RV32-LETTER: first letter should be 'e', 'i' or 'g' But rv32e is a vali

[PATCH] D45284: [RISCV] More validations on the input value of -march=

asb added a comment. Based on Andrew's response (thanks Kito for sending the query) it looks like GCC accepting lowercase only is intentional, and we should follow that. In which case, it might be an improvement to reject uppercase letters in the ISA string with a message saying that only lower

[PATCH] D44888: [RISCV] Default enable linker relaxation and add -mrelax, -mno-relax flags

asb added a comment. Could you please add a test? Given that the current version of https://reviews.llvm.org/D44886 enables linker relaxation by default in the backend, shouldn't -mno-relax cause -relax to be set? Repository: rC Clang https://reviews.llvm.org/D44888 _

[PATCH] D44888: [RISCV] Default enable linker relaxation and add -mrelax, -mno-relax flags

asb added a comment. In https://reviews.llvm.org/D44888#1058257, @asb wrote: > Could you please add a test? Given that the current version of > https://reviews.llvm.org/D44886 enables linker relaxation by default in the > backend, shouldn't -mno-relax cause -relax to be set? Sorry, I misready

[PATCH] D39963: [RISCV][RFC] Add initial RISC-V target and driver support

asb created this revision. Herald added subscribers: jordy.potman.lists, simoncook, johnrusso, rbar, mgorny. I'm marking this as an RFC as I'd initially like to get feedback on the testing approach and structure of this patch (is this about the right granularity or would you prefer to start wit

[PATCH] D40023: [RISCV] Implement ABI lowering

asb created this revision. Herald added subscribers: jordy.potman.lists, rbar, arichardson. RISCVABIInfo is implemented in terms of XLen, supporting both RV32 and RV64. Unfortunately we need to count argument registers in the frontend in order to determine when to emit signext and zeroext attrib

[PATCH] D39963: [RISCV][RFC] Add initial RISC-V target and driver support

asb added inline comments. Comment at: lib/Driver/ToolChains/RISCV.cpp:86 +CmdArgs.push_back("-lc"); +CmdArgs.push_back("-lgloss"); +CmdArgs.push_back("--end-group"); apazos wrote: > mgrang wrote: > > How about if our sysroot is linux (as opposed to e

[PATCH] D40023: [RISCV] Implement ABI lowering

asb added inline comments. Comment at: lib/CodeGen/TargetInfo.cpp:8858 + else +NeededArgGPRs = 1; + efriedma wrote: > It looks like the ABI says there's a special rule for varargs here? You're right, I neglected vararg calls. Now addressed and test cases add

[PATCH] D40023: [RISCV] Implement ABI lowering

asb updated this revision to Diff 123020. asb marked an inline comment as done. asb added a comment. Updated to address review comments. I've added some extra test coverage that demonstrates that argument lowering happens the same once registers are exhausted, as well as more coverage around var

[PATCH] D39963: [RISCV][RFC] Add initial RISC-V target and driver support

asb updated this revision to Diff 123229. asb marked an inline comment as done. asb added a comment. Consider this a WIP update. This is not yet ready for merging, but could still benefit from feedback. This update adds support for RISC-V to the Linux toolchain driver, which includes support fo

[PATCH] D39963: [RISCV][RFC] Add initial RISC-V target and driver support

asb marked 4 inline comments as done. asb added inline comments. Comment at: lib/Driver/ToolChains/RISCV.cpp:86 +CmdArgs.push_back("-lc"); +CmdArgs.push_back("-lgloss"); +CmdArgs.push_back("--end-group"); asb wrote: > apazos wrote: > > mgrang wrote: >

[PATCH] D40256: [ARM] disable FPU features when using soft floating point.

asb added subscribers: llvm-commits, asb. asb added a comment. It would have been much cleaner if it worked as @efriedma suggests and -mfloat-abi was only concerned with the ABI (as its name would suggest), but sadly the -mfloat-abi=soft option seems to be defined in GCC to control more than ju

[PATCH] D145999: [RISCV] Reserve X18 by default for Android

asb added inline comments. Comment at: clang/test/Driver/riscv-fixed-x-register.c:343 + +// Check that x18 is reserved on Android by default +// RUN: %clang --target=riscv64-linux-android -### %s 2> %t samitolvanen wrote: > This seems redundant. Isn't the LLVM co

[PATCH] D145999: [RISCV] Reserve X18 by default for Android

asb accepted this revision. asb added a comment. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D145999/new/ https://reviews.llvm.org/D145999 ___ cfe-commits mailing list cfe-commits@lists.llvm.org h

[PATCH] D145564: [clang][docs] Clarify the semantics of -fexceptions

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGf47404b012d6: [clang][docs] Clarify the semantics of -fexceptions (authored by asb). Herald added a project: clang. Repository: rG LLVM Github Mon

[PATCH] D145070: [clang][RISCV][test] Add test coverage for _Float16 ABI lowering

This revision was automatically updated to reflect the committed changes. Closed by commit rGa7e13d6f1b49: [clang][RISCV][test] Add test coverage for _Float16 ABI lowering (authored by asb). Herald added a subscriber: jobnoorman. Herald added a project: clang. Repository: rG LLVM Github Monorep

[PATCH] D145074: [clang][RISCV] Fix ABI lowering for _Float16 for FP ABIs

asb updated this revision to Diff 505575. asb added a comment. Herald added a subscriber: jobnoorman. Rebase. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D145074/new/ https://reviews.llvm.org/D145074 Files: clang/docs/ReleaseNotes.rst clang/lib/CodeGen/TargetInfo.cpp clang/test/

[PATCH] D145074: [clang][RISCV] Fix ABI lowering for _Float16 for FP ABIs

asb added inline comments. Comment at: clang/test/CodeGen/RISCV/riscv64-abi.c:1909 - NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: -// LP64F: {{.*}} kito-cheng wrote: > This seems removed accidentally, I saw

[PATCH] D146054: [RISCV] Add -print-supported-marchs and -march=help support

asb added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:153 + std::set TempSet(Cmp); + for (auto E : SupportedExtensions) +TempSet.insert(E); craig.topper wrote: > Question for the community. Should we maintain SupportedExtensions in the >

[PATCH] D143436: [clangd] Move standard options adaptor to CommandMangler

asb added a comment. This broke `-DBUILD_SHARED_LIBS=True` builds - I committed rG482d22d05a4a30a4f8594273bd359f7d311c9d4c to fix it. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.or

[PATCH] D146451: [RISCV] Replace RISCV->RISC-V in strings.

asb added a comment. The logic I saw with the pass names is that the backend for the RISC-V architecture is called "RISCV". But I've got no objection to changing. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D146451/new/ https://reviews.llvm.org/D

[PATCH] D146463: [CodeGen][RISCV] Change Shadow Call Stack Register to S11

asb added a comment. In principle I think this is good, but I see two considerations: 1. Sam was right that there's an ability to change the register after the fact, but 2.5 years have passed since then. We should make a good faith attempt to see if any downstream users are relying on the curre

[PATCH] D143570: [RISCV][MC] Add support for RV64E

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGc39dd7c1db97: [RISCV][MC] Add support for RV64E (authored by jobnoorman, committed by asb). Herald added a project: clang. Herald added a subscriber:

[PATCH] D143570: [RISCV][MC] Add support for RV64E

asb added a comment. Apologies, the commited version of this patch missed the clang/test/Driver/riscv-arch.c change. rGe54cdd058e223bd62840e901b8b462c011d2fae5 committed to fix this. Repository: rG LLVM Github Monorepo

[PATCH] D142326: [clang][RISCV][test] Add test cases for empty structs and the FP calling conventions

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGa742511cbe9a: [clang][RISCV][test] Add test cases for empty structs and the FP calling… (authored by asb). Herald added a subscriber: jobnoorman. Re

[PATCH] D145074: [clang][RISCV] Fix ABI lowering for _Float16 for FP ABIs

This revision was not accepted when it landed; it landed in state "Needs Review". This revision was automatically updated to reflect the committed changes. Closed by commit rG938deaad8ac9: [clang][RISCV] Fix ABI lowering for _Float16 for FP ABIs (authored by asb). Repository: rG LLVM Github Mo

[PATCH] D146449: [RISCV] Replace RISCV -> RISC-V in comments. NFC

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D146449/new/ https://reviews.llvm.org/D146449 ___ cfe-

[PATCH] D146451: [RISCV] Replace RISCV->RISC-V in strings.

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. Not as compelling as user facing strings or comments that clearly refer to the RISC-V ISA rather than the "RISCV" LLVM backend. But I don't really see a good reason not to be consistent. LGTM. Rep

[PATCH] D146463: [CodeGen][RISCV] Change Shadow Call Stack Register to S11

asb added a comment. I've flagged this proposed change on Discourse (more the fact we're looking to change it, rather than the precise register we end up with). Repository: rG LLVM Github Monorepo

[PATCH] D146946: [RISCV][MC] Add support for experimental zicond extension

asb created this revision. asb added reviewers: reames, craig.topper. Herald added subscribers: jobnoorman, luke, wingo, pmatos, VincentWu, vkmr, frasercrmck, jdoerfert, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck,

[PATCH] D146946: [RISCV][MC] Add support for experimental zicond extension

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGd3291c692c0a: [RISCV][MC] Add support for the experimental zicond extension (authored by asb). Repository: rG LLVM Github Monorepo CHANGES SINCE

[PATCH] D144853: [Clang][RISCV] Add CMake options to configure default CPU

asb added a comment. If this is a useful thing to have, would it make more sense as a target-independent option? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D144853/new/ https://reviews.llvm.org/D144853 __

[PATCH] D142373: [Utils] Add --full-function-signature to update_cc_test_checks.py to match return type as well as args

asb abandoned this revision. asb added a comment. Abandoned in favour of https://reviews.llvm.org/D144963 which rebases this logic on top of the new `--version` support. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D142373/new/ https://reviews.llv

[PATCH] D145074: [clang][RISCV] Fix ABI lowering for _Float16 for FP ABIs

asb created this revision. asb added reviewers: kito-cheng, jrtc27, reames, craig.topper. Herald added subscribers: luke, wingo, pmatos, VincentWu, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogf

[PATCH] D145125: [RISCV] Make D extension imply F extension.

asb accepted this revision. asb added a comment. I think this is in line with how we now handle implication of specs - when the code was first written IIRC we were much stricter. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D145125/new/ https://re

[PATCH] D145164: [clang][RISCV] Enable -fasynchronous-unwind-tables by default on Linux

asb added a subscriber: jobnoorman. asb added a comment. Funnily enough, @jobnoorman and I were just discussion something related to this, how `-fexceptions` doesn't seem to enable unwind tables as you'd expect. This change hides that issue in the common case you're targeting Linux, but I've fi

[PATCH] D141672: [RISCV] Support vector crypto extension ISA string and assembly

asb added a comment. In D141672#4177044 , @craig.topper wrote: > I guess the question is whether we should update to the most recent now or > land this first. I think updating to the most recent would make sense. Review bandwidth is limited, and it do

[PATCH] D145564: [clang][docs] Clarify the semantics of -fexceptions

asb created this revision. asb added a reviewer: efriedma. Herald added subscribers: wingo, pmatos, sameer.abuasal. Herald added a project: All. asb requested review of this revision. As noted in #6126 the documentation for `-fexceptions` appear

[PATCH] D145564: [clang][docs] Clarify the semantics of -fexceptions

asb added a comment. What do you think about e.g. "Allow exceptions to be thrown through Clang compiled stack frames (on many targets, this will enable unwind information for functions that might have an exception thrown through them. This is on by default in x86-64"? Or were you thinking of so

[PATCH] D145564: [clang][docs] Clarify the semantics of -fexceptions

asb added a comment. I don't see anything x86_64 specific for `OPT_fexceptions` handling in clang/lib/Driver/ToolChains/Clang.cpp. So perhaps "For most targets, this is enabled by default for C++." It's disabled for the ps4/ps5 toolchains and xcore, hence the "most targets" qualifier. CHANGES

[PATCH] D145809: [RISCV] Error if F and Zfinx extensions are specified together.

asb added a comment. The change itself looks good to me, but we have the same issue for D and Zdinx as well. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D145809/new/ https://reviews.llvm.org/D145809 __

[PATCH] D145809: [RISCV] Error if F and Zfinx extensions are specified together.

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. LGTM, thanks! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D145809/new/ https://reviews.llvm.org/D145809

[PATCH] D145817: [RISCV] Consistently place single quotes around extension names in erro messages.

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. LGTM, thanks. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D145817/new/ https://reviews.llvm.org/D145817

[PATCH] D145817: [RISCV] Consistently place single quotes around extension names in erro messages.

asb added a comment. erro => error in the patch title though! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D145817/new/ https://reviews.llvm.org/D145817 ___ cfe-commits mailing list cfe-commits@lists.llv

[PATCH] D121670: [RISCV] Add zihintntl instructions

asb added a comment. In D121670#4192158 , @joshua-arch1 wrote: > It seems that llvm implementation is different from Binutils/GCC. Binutils > didn't regard ntl instructions as aliases of add since encoding space is > reserved for HINT instructions. Ho

[PATCH] D121670: [RISCV] Add zihintntl instructions

asb added a comment. I've created a PR on the ISA manual to try to clarify the confusing overloaded use of the term "reserved" https://github.com/riscv/riscv-isa-manual/pull/990 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D121670/new/ https://rev

[PATCH] D145564: [clang][docs] Clarify the semantics of -fexceptions

asb updated this revision to Diff 505060. asb added a comment. Adjust wording based on discussion. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D145564/new/ https://reviews.llvm.org/D145564 Files: clang/docs/CommandGuide/clang.rst Index: clang/docs/CommandGuide/clang.rst ==

[PATCH] D153170: [RISCV] Sort the extensions in SupportedExtensions and SupportedExperimentalExtensions.

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D153170/new/ https://reviews.llvm.org/D153170 ___ cfe-

[PATCH] D153170: [RISCV] Sort the extensions in SupportedExtensions and SupportedExperimentalExtensions.

asb added a comment. OK, if this patch is going to verify the table is sorted then SupportedExtensions and SupportedExperimentalExtensions probably deserve a comment to explicitly note they must be kept in sort order. Otherwise, still LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE

[PATCH] D149246: [RISCV] Relax rules for ordering s/z/x prefixed extensions in ISA naming strings

asb added a comment. Herald added a subscriber: wangpc. All feedback so far has been positive and this has two LGTMs, but I also recognise this patch has been left for a while. Heads up that I intend to commit this towards the end of the working day Monday UK time unless anyone has any objectio

[PATCH] D149246: [RISCV] Relax rules for ordering s/z/x prefixed extensions in ISA naming strings

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG6101d720cb49: [RISCV] Relax rules for ordering s/z/x prefixed extensions in ISA naming strings (authored by asb). Changed prior to commit: https:/

[PATCH] D153836: [RISCV] Bump vector crypto to v1.0.0-rc1

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. Agreed that looking at https://github.com/riscv/riscv-crypto/compare/v20230531...v20230620 there are no changes that need to be reflected on the LLVM side beyond the version bump here. LGTM Repos

[PATCH] D149248: [RISCV][MC] MC layer support for the experimental zacas extension

asb updated this revision to Diff 535372. asb edited the summary of this revision. asb added a comment. Herald added a subscriber: wangpc. Update to 1.0-rc1 (no code changes needed). CHANGES SINCE LAST ACTION https://reviews.llvm.org/D149248/new/ https://reviews.llvm.org/D149248 Files: cla

[PATCH] D147179: [RISCV] Bump I, F, D, and A extension versions to 20191214 spec version

asb added a comment. I've added a couple of inline comments, but otherwise this seems fine to me. I'd suggest updating the patch description to reference Philip's documentation patch (which was posted soon after this), and also to explain why there are no codegen changes (I think "Either change

[PATCH] D147179: [RISCV] Bump I, F, D, and A extension versions to 20191214 spec version

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. LGTM, thanks (though see minor note about tweaking commit message to clarify the change). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147179/new/ h

[PATCH] D147261: [RISCV] Add Zicsr and Zifencei to CPUs in RISCVProcessors.td.

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. LGTM. I also understand that Rocket and SCR-1 support zicsr and zifencei in all standard configurations (and their respective repos seem to confirm this). Repository: rG LLVM Github Monorepo CHA

[PATCH] D147610: [RISCV][MC] Add support for experimental Zfbfmin extension

asb created this revision. asb added reviewers: reames, craig.topper. Herald added subscribers: jobnoorman, luke, wingo, pmatos, VincentWu, vkmr, frasercrmck, jdoerfert, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck,

[PATCH] D147611: [RISCV][MC] Add support for experimental Zvfbfmin extension

asb created this revision. asb added reviewers: reames, craig.topper. Herald added subscribers: jobnoorman, luke, wingo, pmatos, VincentWu, vkmr, frasercrmck, jdoerfert, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck,

[PATCH] D147612: [RISCV][MC] Add support for experimental Zvfbfwma extension

asb created this revision. asb added reviewers: reames, craig.topper. Herald added subscribers: jobnoorman, luke, wingo, pmatos, VincentWu, vkmr, frasercrmck, jdoerfert, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck,

[PATCH] D147610: [RISCV][MC] Add support for experimental Zfbfmin extension

asb updated this revision to Diff 511080. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147610/new/ https://reviews.llvm.org/D147610 Files: clang/test/Preprocessor/riscv-target-features.c llvm/docs/RISCVUsage.rst llvm/docs/ReleaseNotes.rst llvm/lib/Support/RISCVISAInfo.cpp llvm

[PATCH] D147611: [RISCV][MC] Add support for experimental Zvfbfmin extension

asb updated this revision to Diff 511081. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147611/new/ https://reviews.llvm.org/D147611 Files: clang/test/Preprocessor/riscv-target-features.c llvm/docs/RISCVUsage.rst llvm/docs/ReleaseNotes.rst llvm/lib/Support/RISCVISAInfo.cpp llvm

[PATCH] D147612: [RISCV][MC] Add support for experimental Zvfbfwma extension

asb updated this revision to Diff 511082. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147612/new/ https://reviews.llvm.org/D147612 Files: clang/test/Preprocessor/riscv-target-features.c llvm/docs/RISCVUsage.rst llvm/docs/ReleaseNotes.rst llvm/lib/Support/RISCVISAInfo.cpp llvm

[PATCH] D146463: [CodeGen][RISCV] Change Shadow Call Stack Register to X3

asb added a comment. In D146463#4247050 , @paulkirth wrote: > @asb, @craig.topper, @jrtc27 Are there any remaining considerations for us > here? From the discussions in psABI and sig-toolchain, I think we have a > consensus that this is the approach we

[PATCH] D146463: [CodeGen][RISCV] Change Shadow Call Stack Register to X3

asb added a comment. Ok, looks like the consensus I thought we had isn't quite there on the psABI thread - Andrew Waterman has some concerns. We should let that discussion play out some more. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D146463/ne

[PATCH] D146463: [CodeGen][RISCV] Change Shadow Call Stack Register to X3

asb accepted this revision. asb added a comment. In D146463#4255927 , @paulkirth wrote: > @asb Are we happy with the state of consensus w.r.t. using `x3`? I think the > lingering concerns from the psABI discussion have been resolved. Yes, all LGTM now.

[PATCH] D147986: [RISCV] Print a better error message when a rv32 CPU is used on rv64 and vice versa.

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147986/new/ https://reviews.llvm.org/D147986 ___ cfe-

[PATCH] D147978: [RISCV] Remove getCPUFeaturesExceptStdExt.

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147978/new/ https://reviews.llvm.org/D147978 ___ cfe-

[PATCH] D147935: [RISCV] Add SiFive extension support

asb added inline comments. Comment at: clang/include/clang/Support/RISCVVIntrinsicUtils.h:465 RVV_REQ_FullMultiply = 1 << 1, + RVV_REQ_xsfvcp = 1 << 2, Nit: It would better match the surrounding capitalisation to call this RVV_REQ_Xsfvcp Repository: rG

[PATCH] D132819: [RISCV] Add MC support of RISCV zcmp Extension

asb added inline comments. Comment at: clang/test/Preprocessor/riscv-target-features.c:51 // CHECK-NOT: __riscv_zcf {{.*$}} +// CHECK-NOT: __riscv_zcmp // CHECK-NOT: __riscv_h {{.*$}} jrtc27 wrote: > Does this really belong in an MC patch? We typically do inclu

[PATCH] D148034: [clang][driver] Disable GP relaxation with RISC-V ShadowCallStack

asb added a comment. Will `--[no-]relax-gp` make its way into a minor gcc point release or do we need to wait for the next major release? In terms of this breaking GNU users - isn't it the case that without this option, they may get silently broken code when using the shadow call stack? Breaki

[PATCH] D148066: [RISCV] Add Smaia and Ssaia extensions support

asb added a comment. This extension doesn't appear to be ratified but you've listed it in the table of ratified extensions and treated it as a ratified extension in RISCVISAInfo.cpp. I know that given we don't do checking for CSR names the distinction feels a bit academic, but I don't think thi

[PATCH] D147610: [RISCV][MC] Add support for experimental Zfbfmin extension

asb updated this revision to Diff 512743. asb edited the summary of this revision. asb added a comment. Rebase and use the new encoding suggested in https://github.com/riscv/riscv-bfloat16/issues/33 - hoping for the commits that alter the encoding to be pushed to the spec repo and a new PDF (wit

[PATCH] D147611: [RISCV][MC] Add support for experimental Zvfbfmin extension

asb updated this revision to Diff 512744. asb added a comment. Rebase. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147611/new/ https://reviews.llvm.org/D147611 Files: clang/test/Preprocessor/riscv-target-features.c llvm/docs/RISCVUsage.rst llvm/docs/ReleaseNotes.rst llvm/lib/

[PATCH] D147612: [RISCV][MC] Add support for experimental Zvfbfwma extension

asb updated this revision to Diff 512745. asb added a comment. Rebase CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147612/new/ https://reviews.llvm.org/D147612 Files: clang/test/Preprocessor/riscv-target-features.c llvm/docs/RISCVUsage.rst llvm/docs/ReleaseNotes.rst llvm/lib/S

[PATCH] D148066: [RISCV] Add Smaia and Ssaia extensions support

asb added a comment. In D148066#4262379 , @reames wrote: > I would be fine landing this as experimental before ratification. I see no > real downside to doing that My concern would be that as we don't gate CSR names on enabling the relevant extension,

[PATCH] D148034: [clang][driver] Disable GP relaxation with RISC-V ShadowCallStack

asb added a comment. In D148034#4262991 , @MaskRay wrote: > In D148034#4260376 , @asb wrote: > >> Will `--[no-]relax-gp` make its way into a minor gcc point release or do we >> need to wait for the next major rel

[PATCH] D147612: [RISCV][MC] Add support for experimental Zvfbfwma extension

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGa1455de74d95: [RISCV][MC] Add support for experimental Zvfbfwma extension (authored by asb). Changed prior to commit: https://reviews.llvm.org/D14

[PATCH] D150926: [RISCV] Support LMUL!=1 for __attribute__((riscv_rvv_vector_bits(N)))

asb added inline comments. Comment at: clang/include/clang/Basic/AttrDocs.td:2347 -Only ``*m1_t`` (LMUL=1) types are supported at this time. +For types where LMUL!=1, ``__riscv_v_fixed_vlen`` needs to be scaled by the LMULo +of the type before passing to the attribute. ---

[PATCH] D151547: [RISCV] Remove experimental for zihintntl.

asb added a comment. Is the __riscv_ntl_* interface finalised and agreed? I'm wary of repeating the mistake we made with the V extension where we exposed intrinsics that weren't yet finalised. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D151547/n

[PATCH] D142327: [clang][RISCV] Fix ABI handling of empty structs with hard FP calling conventions in C++

asb added a comment. Herald added a subscriber: jobnoorman. Friendly ping on this (I think mostly directed at @kito-cheng who was hoping to find time to review the linked abi issue ). CHANGES SINCE LAST ACTION https://reviews.l

<    1   2   3   4   >