[clang] [llvm] Enable OpenCL hostcall printf (WIP) (PR #72556)

@@ -170,20 +173,49 @@ static Value *appendString(IRBuilder<> &Builder, Value *Desc, Value *Arg, return callAppendStringN(Builder, Desc, Arg, Length, IsLast); } +static Value *appendVectorArg(IRBuilder<> &Builder, Value *Desc, Value *Arg, + bool

[clang] [llvm] Enable OpenCL hostcall printf (WIP) (PR #72556)

@@ -194,6 +226,8 @@ static void locateCStrings(SparseBitVector<8> &BV, StringRef Str) { SpecPos += 2; continue; } +if (Str.find_first_of("v", SpecPos) != StringRef::npos) ssahasra wrote: I don't think this will work as expected. It can cle

[llvm] [clang] Enable OpenCL hostcall printf (WIP) (PR #72556)

@@ -170,20 +173,49 @@ static Value *appendString(IRBuilder<> &Builder, Value *Desc, Value *Arg, return callAppendStringN(Builder, Desc, Arg, Length, IsLast); } +static Value *appendVectorArg(IRBuilder<> &Builder, Value *Desc, Value *Arg, + bool

[llvm] [clang] Enable OpenCL hostcall printf (WIP) (PR #72556)

@@ -1,12 +1,68 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -cl-std=CL1.2 -triple amdgcn-amd-amdhsa -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -cl-std=CL1.2 -triple amdgcn-amd-amdhsa -mprint

[clang] [AMDGPU] Treat printf as builtin for OpenCL (PR #72554)

@@ -406,5 +410,9 @@ TARGET_BUILTIN(__builtin_amdgcn_cvt_pk_fp8_f32, "iffiIb", "nc", "fp8-insts") TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_bf8_f32, "ifiiIi", "nc", "fp8-insts") TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_fp8_f32, "ifiiIi", "nc", "fp8-insts") +// OpenCL +LANGBUILTIN(p

[clang] [AArch64][SME2] Add PEXT, PSEL builtins for SME2 (PR #72827)

https://github.com/dtemirbulatov created https://github.com/llvm/llvm-project/pull/72827 This change enables PEXT, PSEL builtins for SME2 target. >From 7aa69c9cb936b3883de7922f72ed9417be5a16f5 Mon Sep 17 00:00:00 2001 From: Dinar Temirbulatov Date: Mon, 20 Nov 2023 07:04:18 + Subject: [PAT

[clang] [AArch64][SME2] Add PEXT, PSEL builtins for SME2 (PR #72827)

llvmbot wrote: @llvm/pr-subscribers-clang Author: Dinar Temirbulatov (dtemirbulatov) Changes This change enables PEXT, PSEL builtins for SME2 target. --- Patch is 25.95 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/72827.diff 3 Files Affect

[clang] d572c4c - [PowerPC] Disable float128 on AIX in Clang (#67298)

Author: Qiu Chaofan Date: 2023-11-20T15:20:57+08:00 New Revision: d572c4cdef4b3a2b1f57769233f33a1788f5172e URL: https://github.com/llvm/llvm-project/commit/d572c4cdef4b3a2b1f57769233f33a1788f5172e DIFF: https://github.com/llvm/llvm-project/commit/d572c4cdef4b3a2b1f57769233f33a1788f5172e.diff L

[clang] [PowerPC] Disable float128 on AIX in Clang (PR #67298)

https://github.com/ecnelises closed https://github.com/llvm/llvm-project/pull/67298 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [AArch64][SME2] Enable bfm builtins for sme2 (PR #71927)

@@ -1992,3 +1986,12 @@ let TargetGuard = "sme2" in { def SVADD_SINGLE_X2 : SInst<"svadd[_single_{d}_x2]", "22d", "cUcsUsiUilUl", MergeNone, "aarch64_sve_add_single_x2", [IsStreaming], []>; def SVADD_SINGLE_X4 : SInst<"svadd[_single_{d}_x4]", "44d", "cUcsUsiUilUl", MergeNon

[clang-tools-extra] [clangd] [C++20] [Modules] Introduce initial support for C++20 Modules (PR #66462)

ChuanqiXu9 wrote: @sam-mccall ping https://github.com/llvm/llvm-project/pull/66462 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[lld] [libunwind] [compiler-rt] [libcxxabi] [flang] [lldb] [clang] [llvm] [clang-tools-extra] [libc] [libcxx] [mlir] PR#72453 : Exceeding maximum file name length (PR #72654)

@@ -83,10 +85,29 @@ struct DOTGraphTraitsViewer StringRef Name; }; +static void shortenFileName(std::string &FN, unsigned char len = 250) { + + FN = FN.substr(0, len); + if (nameObj.empty()) +nameObj.push_back(FN); + + else { +for (auto it = nameObj.begin(); it !=

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